參數(shù)資料
型號： L6713A
廠商： Holtek Semiconductor Inc.
英文描述： 2/3 Phase controller with embedded drivers for Intel VR10, VR11 and AMD 6 bit CPUs
中文描述： 2 / 3為英特爾VR10，VR11和AMD的嵌入式驅動器相控制器6位CPU
文件頁數(shù)： 22/64頁
文件大?。?/td> 515K
代理商： L6713A
L6713A
Configuring the device
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Output voltage is programmed through the VID pins: they are inputs of an internal DAC that
is realized by means of a series of resistors providing a partition of the internal voltage
reference. The VID code drives a multiplexer that selects a voltage on a precise point of the
divider. The DAC output is delivered to an amplifier obtaining the voltage reference (i.e. the
set-point of the error amplifier, VREF).
Note:
VID pull-ups / pull-downs, VID voltage thresholds and OUTEN thresholds changes
according to the selected DAC: See Table 4 for details.
Note:
VID pull-ups / pull-downs, VID voltage thresholds and OUTEN thresholds changes
according to the selected DAC: See Table 4 for details.
Table 12. Intel Mode Configuration (See Note).
Pin
Function (1)
Typical Connection
SS / LTBG /
AMD
It allows programming the soft-start time TSS
and also the LTB Technology Gain. See “Soft
start” Section and See “Load Transient Boost
TechnologyTM” Section for details.
RSSOSC Resistor in series to
Signal Diode vs. SSEND pin.
(LTBGain = 2, default value).
VID_SEL
It allows selecting between VR11 DAC or
VR10.x + 6.25mV extended DAC.
Static info, no dynamic changes allowed.
Open: VR11 (
Table 6 ).
Short to SGND: VR10.x
(
Table 7 ).
VID7 to VID0
They allow programming the Output Voltage
according to Table 6 and Table 7.
Dynamic transitions managed, See “Dynamic
VID transitions” Section for details.
Open: Logic “1” (25
A pull-up)
Short to SGND: “0”
SSEND /
PGOOD
Soft Start end signal set free after soft-start has
finished. It only indicates soft-start has finished.
Pull-up to anything lower than
5V.
Table 13. AMD Mode Configuration (See Note).
Pin
Function
Typical Connection
SS / LTBG /
AMD
It allows programming AMD 6 BIT DAC.
Short to SGND.
VID_SEL
Not Applicable
Need to be shorted to SGND.
VID7 / DVID
Pulled high when performing a D-VID transition.
The pin is kept high with a 32 clock cycles delay.
Not Applicable
VID6
Not Applicable
Need to be shorted to SGND.
VID5 to VID0
They allow programming the Output Voltage
according to Table 9.
Dynamic transitions managed, See “Dynamic
VID transitions” Section for details.
Open: “0” (12.5
A pull-down)
Pull-up to V > 1.4V: “1”
SSEND /
PGOOD
Power Good signal set free after soft-start has
finished whenever the output voltage is within
limits.
Pull-up to anything lower than
5V.
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