參數(shù)資料
型號(hào)： KSZ9021GN TR
廠商： Micrel Inc
文件頁(yè)數(shù)： 8/53頁(yè)
文件大?。?/td> 0K
描述： TXRX ETHERNET GB GMII/MII 64MLF
標(biāo)準(zhǔn)包裝： 1,000
類型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 8/8
規(guī)程： 千兆位以太網(wǎng)
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-QFN（8x8）
包裝： 帶卷 (TR)
配用： 576-3873-ND - BOARD EVALUATION FOR KSZ9021GN
Micrel, Inc.
KSZ9021GN
September 2010
16
M9999-091010-1.1
Functional Description: 10Base-T/100Base-TX Transceiver
100Base-TX Transmit
The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, and MLT-3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial
bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized
data is further converted from NRZ-to-NRZI format, and then transmitted in MLT-3 current output. The output current is
set by an external 4.99K
Ω 1% resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX
transmitter.
100Base-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT-3-to-NRZI conversion, data
and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted
pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for
optimization. This is an ongoing process and self-adjusts against environmental changes such as temperature
variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used
to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion
circuit converts the MLT-3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to the GMII/MII format and provided as the input data to the MAC.
Scrambler/De-scrambler (100Base-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference
(EMI) and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift
register (LFSR). The scrambler generates a 2047-bit non-repetitive sequence, and the receiver then de-scrambles the
incoming data stream using the same sequence as at the transmitter.
10Base-T Transmit
The output 10Base-T driver is incorporated into the 100Base-TX driver to allow transmission with the same magnetic.
They are internally wave-shaped and pre-emphasized into typical outputs of 2.5V amplitude. The harmonic contents are
at least 31 dB below the fundamental when driven by an all-ones Manchester-encoded signal.
10Base-T Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit
and a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into
clock signal and NRZ data. A squelch circuit rejects signals with levels less than 300 mV or with short pulse widths in
order to prevent noises at the receive inputs from falsely triggering the decoder. When the input exceeds the squelch
limit, the PLL locks onto the incoming signal and the KSZ9021GN decodes a data frame. The receiver clock is
maintained active during idle periods in between receiving data frames.
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