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參數(shù)資料
| 型號： | KSZ8895MQ |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 58/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ETHERNET SW 5PORT 128-PQFP |
| 標準包裝： | 66 |
| 控制器類型： | 以太網(wǎng)開關(guān)控制器 |
| 接口： | MII |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-PQFP（14x20） |
| 包裝： | 托盤 |
| 配用： | 576-3871-ND - BOARD EVALUATION FOR KSZ8895MQ |
| 其它名稱： | 576-3753 |
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Micrel, Inc.
KSZ8895MQ/RQ/FMQ
The KSZ8895MQ/RQ/FMQ provides the option to insert or remove the priority tagged frame's header at each
individual egress port. This header, consisting of the two-byte VLAN Protocol ID (VPID) and the two-byte Tag Control
Information field (TCI), is also referred to as the IEEE 802.1Q VLAN tag.
Tag Insertion is enabled by bit[2] of the port registers control 0 and the port register control 8 to select which source
port (ingress port) PVID can be inserted on the egress port for ports 1, 2, 3, 4 and 5, respectively. At the egress port,
untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in the port
registers control 3 and control 4 for ports 1, 2, 3, 4 and 5, respectively. The KSZ8895MQ/RQ/FMQ will not add tags
to already tagged packets.
Tag Removal is enabled by bit[1] of the port registers control 0 for ports 1, 2, 3, 4 and 5, respectively. At the egress
port, tagged packets will have their 802.1Q VLAN tags removed. The KSZ8895MQ/RQ/FMQ will not modify untagged
packets.
The CRC is recalculated for both tag insertion and tag removal.
802.1p Priority Field Re-mapping is a QoS feature that allows the KSZ8895MQ/RQ/FMQ to set the “User Priority
Ceiling” at any ingress port by the port register control 2 bit 7. If the ingress packet’s priority field has a higher priority
value than the default tag’s priority field of the ingress port, the packet’s priority field is replaced with the default tag’s
priority field.
DiffServ-Based Priority
DiffServ-based priority uses the ToS registers (registers 144 to 159) in the Advanced Control Registers section. The
ToS priority control registers implement a fully decoded, 128-bit Differentiated Services Code Point (DSCP) register
to determine packet priority from the 6-bit ToS field in the IP header. When the most significant six bits of the ToS
field are fully decoded, 64 code points for DSCP result. These are compared with the corresponding bits in the DSCP
register to determine priority.
Spanning Tree Support
Port 5 is the designated port for spanning tree support.
The other ports (Port 1
Port 4) can be configured in one of the five spanning tree states via “transmit enable,”
“receive enable,” and “l(fā)earning disable” register settings in Registers 18, 34, 50, and 66 for Ports 1, 2, 3, and 4,
respectively. The following description shows the port setting and software actions taken for each of the five
spanning tree states:
Disable state: the port should not forward or receive any packets. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1."
Software action: the processor should not send any packets to the port. The switch may still send specific packets to
the processor (packets that match some entries in the static table with “overriding bit” set) and the processor should
discard those packets. Note: the processor is connected to Port 5 via MII interface. Address learning is disabled on
the port in this state.
Blocking state: only packets to the processor are forwarded. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1"
Software action: the processor should not send any packets to the port(s) in this state. The processor should
program the “Static MAC table” with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit
should also be set so that the switch will forward those specific packets to the processor. Address learning is
disabled on the port in this state.
Listening state: only packets to and from the processor are forwarded. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1.
"Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g.
BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the
processor. The processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details.
Address learning is disabled on the port in this state.
Learning state: only packets to and from the processor are forwarded. Learning is enabled.
Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0.”
March 12, 2014
43
Revision 1.7
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8895MQ_12 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface |
| KSZ8895MQ-EVAL | 功能描述:以太網(wǎng)開發(fā)工具 5-Port 10/100 Ethernet Switch with 1x MII Interface - Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| KSZ8895MQI | 功能描述:以太網(wǎng) IC 5-Port 10/100 Ethernet Switch with 1x MII Interface (Industrial Grade) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8895MQXCA | 功能描述:Ethernet Switch 10/100 Base-T/TX I2C, SPI Interface 128-PQFP (14x20) 制造商:microchip technology 系列:- 包裝:托盤 零件狀態(tài):有效 協(xié)議:以太網(wǎng) 功能:開關(guān) 接口:I2C，SPI 標準:10/100 Base-T/TX 電壓 - 電源:1.8V，2.5V，3.3V 電流 - 電源:129mA 工作溫度:0°C ~ 70°C 封裝/外殼:128-BFQFP 供應(yīng)商器件封裝:128-PQFP（14x20） 標準包裝:66 |
| KSZ8895MQXIA | 功能描述:Ethernet Switch 10/100 Base-T/TX I2C, SPI Interface 128-PQFP (14x20) 制造商:microchip technology 系列:- 包裝:托盤 零件狀態(tài):有效 協(xié)議:以太網(wǎng) 功能:開關(guān) 接口:I2C，SPI 標準:10/100 Base-T/TX 電壓 - 電源:1.8V，2.5V，3.3V 電流 - 電源:129mA 工作溫度:-40°C ~ 85°C 封裝/外殼:128-BFQFP 供應(yīng)商器件封裝:128-PQFP（14x20） 標準包裝:66 |
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