參數(shù)資料
型號: KSZ8873FLLI
廠商: Micrel Inc
文件頁數(shù): 73/115頁
文件大?。?/td> 0K
描述: IC ETHERNET SWITCH 3PORT 64LQFP
產(chǎn)品培訓模塊: KSZ8873 Ethernet Switches
標準包裝: 160
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: MII
電源電壓: 1.8V,2.5V,3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-LQFP(10x10)
包裝: 托盤
其它名稱: 576-3632
KSZ8873FLLI-ND
Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
60
Revision 1.6
Register 15 (0x0F): Global Control 13
Bit
Name
R/W
Description
Default
7-3
PHY Address
R/W
00000 : N/A
00001 : Port 1 PHY address is 0x1
00010 : Port 1 PHY address is 0x2
11101 : Port 1 PHY address is 0x29
11110 : N/A
11111 : N/A
Note:
Port 2 PHY address = (Port 1 PHY address) + 1
00001
2-0
Reserved
RO
Reserved
Do not change the default values.
000
Port Registers (Registers 16 – 95)
The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are
the same for all ports, but the address for each port is different, as indicated.
Register 16 (0x10): Port 1 Control 0
Register 32 (0x20): Port 2 Control 0
Register 48 (0x30): Port 3 Control 0
Bit
Name
R/W
Description
Default
7
Broadcast Storm
Protection Enable
R/W
=1, Enable broadcast storm protection for ingress packets on port
=0, Disable broadcast storm protection
0
6
DiffServ Priority
Classification
Enable
R/W
=1, Enable DiffServ priority classification for ingress packets (IPv4) on port
=0, Disable DiffServ function
0
5
802.1p Priority
Classification
Enable
R/W
=1, Enable 802.1p priority classification for ingress packets on port
=0, Disable 802.1p
0
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