參數(shù)資料
型號： KSZ8873FLLI
廠商： Micrel Inc
文件頁數(shù)： 52/115頁
文件大小： 0K
描述： IC ETHERNET SWITCH 3PORT 64LQFP
產(chǎn)品培訓(xùn)模塊： KSZ8873 Ethernet Switches
標(biāo)準(zhǔn)包裝： 160
控制器類型： 以太網(wǎng)開關(guān)控制器
接口： MII
電源電壓： 1.8V，2.5V，3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
其它名稱： 576-3632
KSZ8873FLLI-ND
Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
41
Revision 1.6
All the packets received on port A and transmitted on port B are mirrored on the sniffer port. To turn on the “AND”
feature, set Register 5 bit [0] to ‘1’. For example, port 1 is programmed to be “receive sniff”, port 2 is programmed to
be “transmit sniff”, and port 3 is programmed to be the “sniffer port”. A packet received on port 1 is destined to port 2
after the internal lookup. The KSZ8873MLL/FLL/RLL forwards the packet to both port 2 and port 3.
Multiple ports can be selected as “receive sniff” or “transmit sniff”. In addition, any port can be selected as the “sniffer
port”. All these per port features can be selected through Registers 17, 33, and 49 for ports 1, 2 and 3, respectively.
Rate Limiting Support
The KSZ8873MLL/FLL/RLL provides a fine resolution hardware rate limiting from 64Kbps to 99Mbps. The rate step is
64Kbps when the rate range is from 64Kbps to 960Kbps and 1Mbps for 1Mbps to 100Mbps(100BT) or to 10Mbps(10BT)
(refer to Data Rate Limit Table). The rate limit is independently on the “receive side” and on the “transmit side” on a per
port basis. For 10BASE-T, a rate setting above 10 Mbps means the rate is not limited. On the receive side, the data
receive rate for each priority at each port can be limited by setting up Ingress Rate Control Registers. On the transmit
side, the data transmit rate for each priority queue at each port can be limited by setting up Egress Rate Control
Registers. The size of each frame has options to include minimum IFG (Inter Frame Gap) or Preamble byte, in addition to
the data field (from packet DA to FCS).
For ingress rate limiting, KSZ8873MLL/FLL/RLL provides options to selectively choose frames from all types, multicast,
broadcast, and flooded unicast frames. The KSZ8873MLL/FLL/RLL counts the data rate from those selected type of
frames. Packets are dropped at the ingress port when the data rate exceeds the specified rate limit.
For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic. Inter
frame gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of each output
priority queue is limited by the egress rate specified.
If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the
output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control
will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping at the
ingress end, and may be therefore slightly less than the specified egress rate.
To reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth.
Unicast MAC Address Filtering
The unicast MAC address filtering function works in conjunction with the static MAC address table. First, the static MAC
address table is used to assign a dedicated MAC address to a specific port. If a unicast MAC address is not recorded in
the static table, it is also not learned in the dynamic MAC table. The KSZ8873MLL/FLL/RLL is then configured with the
option to either filter or forward unicast packets for an unknown MAC address. This option is enabled and configured in
Register 14.
This function is useful in preventing the broadcast of unicast packets that could degrade the quality of the port in
applications such as voice over Internet Protocol (VoIP).
Configuration Interface
The KSZ8873MLL/FLL/RLL can operate as both a managed switch and an unmanaged switch.
In unmanaged mode, the KSZ8873MLL/FLL/RLL is typically programmed using an EEPROM. If no EEPROM is present,
the KSZ8873MLL/FLL/RLL is configured using its default register settings. Some default settings are configured via strap-
in pin options. The strap-in pins are indicated in the “Pin Description and I/O Assignment” table.
I
2C Master Serial Bus Configuration
With an additional I
2C (“2-wire”) EEPROM, the KSZ8873MLL/FLL/RLL can perform more advanced switch features like
“broadcast storm protection” and “rate control” without the need of an external processor.
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