參數(shù)資料
型號(hào)： KSZ8851-16MLL-EVAL
廠商： Micrel Inc
文件頁數(shù)： 45/84頁
文件大?。?/td> 0K
描述： BOARD EVALUATION KSZ8851-16MLL
產(chǎn)品培訓(xùn)模塊： KSZ8851 10/100 Embedded Controllers
標(biāo)準(zhǔn)包裝： 1
系列： LinkMD®
主要目的： 接口，以太網(wǎng)控制器（PHY 和 MAC）
嵌入式： 否
已用 IC / 零件： KSZ8851-16MLL
主要屬性： 1 個(gè)端口，100BASE-TX/10BASE-T
次要屬性： 8/16 位接口，LinkMD 線纜診斷
已供物品： 板，文檔
產(chǎn)品目錄頁面： 1081 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： 576-3438-ND - IC CTLR MAC/PHY NON PCI 128PQFP
576-3253-ND - IC CTLR MAC/PHY NON-PCI 128-PQFP
576-3252-ND - IC CTLR MAC/PHY NON-PCI 48-LQFP
其它名稱： 576-3292
Micrel, Inc.
KSZ8851-16MLL/MLLI
March 11, 2014
5
Revision 2.2
Wakeup Frame 1 CRC0 Register (0x40 – 0x41): WF1CRC0 ...................................................................................... 44
Wakeup Frame 1 CRC1 Register (0x42 – 0x43): WF1CRC1 ...................................................................................... 45
Wakeup Frame 1 Byte Mask 0 Register (0x44 – 0x45): WF1BM0 .............................................................................. 45
Wakeup Frame 1 Byte Mask 1 Register (0x46 – 0x47): WF1BM1 .............................................................................. 45
Wakeup Frame 1 Byte Mask 2 Register (0x48 – 0x49): WF1BM2 .............................................................................. 45
Wakeup Frame 1 Byte Mask 3 Register (0x4A – 0x4B): WF1BM3.............................................................................. 45
0x4C – 0x4F: Reserved ................................................................................................................................................ 45
Wakeup Frame 2 CRC0 Register (0x50 – 0x51): WF2CRC0 ...................................................................................... 45
Wakeup Frame 2 CRC1 Register (0x52 – 0x53): WF2CRC1 ...................................................................................... 46
Wakeup Frame 2 Byte Mask 0 Register (0x54 – 0x55): WF2BM0 .............................................................................. 46
Wakeup Frame 2 Byte Mask 1 Register (0x56 – 0x57): WF2BM1 .............................................................................. 46
Wakeup Frame 2 Byte Mask 2 Register (0x58 – 0x59): WF2BM2 .............................................................................. 46
Wakeup Frame 2 Byte Mask 3 Register (0x5A – 0x5B): WF2BM3.............................................................................. 46
0x5C – 0x5F: Reserved ................................................................................................................................................ 46
Wakeup Frame 3 CRC0 Register (0x60 – 0x61): WF3CRC0 ...................................................................................... 46
Wakeup Frame 3 CRC1 Register (0x62 – 0x63): WF3CRC1 ...................................................................................... 47
Wakeup Frame 3 Byte Mask 0 Register (0x64 – 0x65): WF3BM0 .............................................................................. 47
Wakeup Frame 3 Byte Mask 1 Register (0x66 – 0x67): WF3BM1 .............................................................................. 47
Wakeup Frame 3 Byte Mask 2 Register (0x68 – 0x69): WF3BM2 .............................................................................. 47
Wakeup Frame 3 Byte Mask 3 Register (0x6A – 0x6B): WF3BM3.............................................................................. 47
0x6C – 0x6F: Reserved ................................................................................................................................................ 47
Transmit Control Register (0x70 – 0x71): TXCR.......................................................................................................... 48
Transmit Status Register (0x72 – 0x73): TXSR ........................................................................................................... 49
Receive Control Register 1 (0x74 – 0x75): RXCR1 ..................................................................................................... 49
Receive Control Register 2 (0x76 – 0x77): RXCR2 ..................................................................................................... 50
TXQ Memory Information Register (0x78 – 0x79): TXMIR .......................................................................................... 51
0x7A – 0x7B: Reserved ................................................................................................................................................ 51
Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR ............................................................................. 51
Receive Frame Header Byte Count Register (0x7E – 0x7F): RXFHBCR.................................................................... 52
TXQ Command Register (0x80 – 0x81): TXQCR ........................................................................................................ 52
RXQ Command Register (0x82 – 0x83): RXQCR........................................................................................................ 53
TX Frame Data Pointer Register (0x84 – 0x85): TXFDPR .......................................................................................... 54
RX Frame Data Pointer Register (0x86 – 0x87): RXFDPR.......................................................................................... 54
0x88 – 0x8B: Reserved ................................................................................................................................................ 55
RX Duration Timer Threshold Register (0x8C – 0x8D): RXDTTR ............................................................................... 55
RX Data Byte Count Threshold Register (0x8E – 0x8F): RXDBCTR .......................................................................... 55
Interrupt Enable Register (0x90 – 0x91): IER .............................................................................................................. 55
Interrupt Status Register (0x92 – 0x93): ISR ............................................................................................................... 56
0x94 – 0x9B: Reserved ................................................................................................................................................ 57
RX Frame Count & Threshold Register (0x9C – 0x9D): RXFCTR............................................................................... 57
TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR ................................................................................. 57
MAC Address Hash Table Register 0 (0xA0 – 0xA1): MAHTR0.................................................................................. 58
MAC Address Hash Table Register 1 (0xA2 – 0xA3): MAHTR1.................................................................................. 58
MAC Address Hash Table Register 2 (0xA4 – 0xA5): MAHTR2.................................................................................. 58
MAC Address Hash Table Register 3 (0xA6 – 0xA7): MAHTR3.................................................................................. 58
0xA8 – 0xAF: Reserved................................................................................................................................................ 58
Flow Control Low Watermark Register (0xB0 – 0xB1): FCLWR.................................................................................. 58
Flow Control High Watermark Register (0xB2 – 0xB3): FCHWR ................................................................................ 59
Flow Control Overrun Watermark Register (0xB4 – 0xB5): FCOWR........................................................................... 59
0xB6 – 0xBF: Reserved................................................................................................................................................ 59
Chip ID and Enable Register (0xC0 – 0xC1): CIDER .................................................................................................. 59
0xC2 – 0xC5: Reserved ............................................................................................................................................... 59
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KSZ8851-16MLL-EVAL 制造商:Micrel Inc 功能描述:BOARD EVALUATION FOR KSZ8851-16MLL
KSZ8851-16MLLI 功能描述:以太網(wǎng) IC 10/100BT Ethernet MAC + PHY with Generic (8, 16-bit) Bus Interface (I-Temp, Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8851-16MLLI TR 功能描述:以太網(wǎng) IC 10/100BT Ethernet MAC + PHY with Generic (8, 16-bit) Bus Interface (I-Temp, Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8851-16MLLJ 功能描述:以太網(wǎng) IC Single-Port Ethernet MAC Controller with 8/16-Bit Non-PCI Interface (125C support) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8851-16MLLJ_10 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface
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