參數(shù)資料
型號(hào)： KSZ8041RNLU TR
廠商： Micrel Inc
文件頁數(shù)： 8/54頁
文件大小： 0K
描述： TXRX PHY 100BASE TX 3.3V 32QFN
標(biāo)準(zhǔn)包裝： 1
類型： PHY 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： MII，RMII
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，32-MLF?
供應(yīng)商設(shè)備封裝： 32-MLF?（5x5）
包裝： 標(biāo)準(zhǔn)包裝
配用： 576-3863-ND - BOARD EVALUATION FOR KSZ8041RNL
其它名稱： 576-3745-6
Micrel, Inc.
KSZ8041NL/RNL
September 2010
16
M9999-090910-1.4
Pin Description – KSZ8041RNL
Pin Number
Pin Name
Type
(1)
Pin Function
1
GND
Gnd
Ground
2
VDDPLL_1.8
P
1.8V analog VDD
3
VDDA_3.3
P
3.3V analog VDD
4
RX-
I/O
Physical receive or transmit signal (- differential)
5
RX+
I/O
Physical receive or transmit signal (+ differential)
6
TX-
I/O
Physical transmit or receive signal (- differential)
7
TX+
I/O
Physical transmit or receive signal (+ differential)
8
XO
O
Crystal feedback – for 25 MHz crystal
This pin is a no connect if oscillator or external clock source is used.
9
XI
I
Crystal / Oscillator / External Clock Input
25MHz +/-50ppm
10
REXT
I/O
Set physical transmit output current
Connect a 6.49K
Ω resistor in parallel with a 100pF capacitor to ground on this
pin. See KSZ8041RNL reference schematics.
11
MDIO
I/O
Management Interface (MII) Data I/O
This pin requires an external 4.7K
Ω pull-up resistor.
12
MDC
I
Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
13
PHYAD0
Ipu/O
The pull-up/pull-down value is latched as PHYADDR[0] during power-up / reset.
See “Strapping Options” section for details.
14
PHYAD1
Ipd/O
The pull-up/pull-down value is latched as PHYADDR[1] during power-up / reset.
See “Strapping Options” section for details.
15
RXD1 /
PHYAD2
Ipd/O
RMII Mode:
RMII Receive Data Output[1]
(2)
/
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[2] during
power-up / reset. See “Strapping Options” section for details.
16
RXD0 /
DUPLEX
Ipu/O
RMII Mode:
RMII Receive Data Output[0]
(2)
/
Config Mode:
Latched as DUPLEX (register 0h, bit 8) during power-up /
reset. See “Strapping Options” section for details.
17
VDDIO_3.3
P
3.3V digital VDD
18
CRS_DV /
CONFIG2
Ipd/O
RMII Mode:
Carrier Sense/Receive Data Valid Output /
Config Mode:
The pull-up/pull-down value is latched as CONFIG2 during
power-up / reset. See “Strapping Options” section for details.
19
REF_CLK
O
50MHz Clock Output
This pin provides the 50MHz RMII reference clock output to the MAC.
20
RX_ER /
ISO
Ipd/O
RMII Mode:
RMII Receive Error Output /
Config Mode:
The pull-up/pull-down value is latched as ISOLATE during
power-up / reset. See “Strapping Options” section for details.
21
INTRP
Opu
Interrupt Output: Programmable Interrupt Output
Register 1Bh is the Interrupt Control/Status Register for programming the
interrupt conditions and reading the interrupt status. Register 1Fh bit 9 sets the
interrupt output to active low (default) or active high.
22
NC
O
No connect
23
TX_EN
I
RMII Transmit Enable Input
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