參數(shù)資料
型號: KSZ8041RNLU TR
廠商: Micrel Inc
文件頁數(shù): 11/54頁
文件大?。?/td> 0K
描述: TXRX PHY 100BASE TX 3.3V 32QFN
標(biāo)準(zhǔn)包裝: 1
類型: PHY 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: MII,RMII
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,32-MLF?
供應(yīng)商設(shè)備封裝: 32-MLF?(5x5)
包裝: 標(biāo)準(zhǔn)包裝
配用: 576-3863-ND - BOARD EVALUATION FOR KSZ8041RNL
其它名稱: 576-3745-6
Micrel, Inc.
KSZ8041NL/RNL
September 2010
19
M9999-090910-1.4
Strapping Options – KSZ8041RNL
Pin Number
Pin Name
Type
(1)
Pin Function
15
14
13
PHYAD2
PHYAD1
PHYAD0
Ipd/O
Ipu/O
The PHY Address is latched at power-up / reset and is configurable to any value from
1 to 7.
The default PHY Address is 00001.
PHY Address bits [4:3] are always set to ‘00’.
18
29
28
CONFIG2
CONFIG1
CONFIG0
Ipd/O
The CONFIG[2:0] strap-in pins are latched at power-up / reset and are defined as
follows:
CONFIG[2:0]
Mode
000
Reserved – not used
001
RMII
010
Reserved – not used
011
Reserved – not used
100
Reserved – not used
101
Reserved – not used
110
Reserved – not used
111
Reserved – not used
20
ISO
Ipd/O
ISOLATE mode
Pull-up = Enable
Pull-down (default) = Disable
During power-up / reset, this pin value is latched into register 0h bit 10.
31
SPEED
Ipu/O
SPEED mode
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
During power-up / reset, this pin value is latched into register 0h bit 13 as the Speed
Select, and also is latched into register 4h (Auto-Negotiation Advertisement) as the
Speed capability support.
16
DUPLEX
Ipu/O
DUPLEX mode
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
During power-up / reset, this pin value is latched into register 0h bit 8 as the Duplex
Mode.
30
NWAYEN
Ipu/O
Nway Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
During power-up / reset, this pin value is latched into register 0h bit 12.
Note:
1.
Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during
power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched high. In this case, it is
recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to ISOLATE mode,
or is not configured with an incorrect PHY Address.
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