參數(shù)資料
型號(hào)： KMC8610VT1333JB
廠商： Freescale Semiconductor
文件頁數(shù)： 63/96頁
文件大小： 0K
描述： IC HOST PROCESS 1333MHZ 783-PBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.333GHz
電壓： 1.025V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Electrical Characteristics
Freescale Semiconductor
66
Figure 41. Minimum Transmitter Timing and Voltage Output Compliance Specifications
2.18.4.3
Differential Receiver (RX) Input Specifications
Table 50 defines the specifications for the differential input at all receivers (RXs). The parameters are specified at the
component pins.
Table 50. Differential Receiver (RX) Input Specifications
Symbol
Parameter
Min
Nom
Max
Units
Comments
UI
Unit interval
399.88
400
400.12
ps
Each UI is 400 ps ± 300 ppm. UI does not account for
Spread Spectrum Clock dictated variations.
See Note 1.
VRX-DIFFp-p
Differential
peak-to-peak
output voltage
0.175
1.200
V
VRX-DIFFp-p = 2*|VRX-D+ – VRX-D–|
See Note 2
TRX-EYE
Minimum
receiver eye
width
0.4
UI
The maximum interconnect media and transmitter
jitter that can be tolerated by the receiver can be
derived as TRX-MAX-JITTER = 1 – TRX-EYE= 0.6 UI.
See Notes 2 and 3
TRX-EYE-MEDIAN-to-MAX
-JITTER
Maximum time
between the jitter
median and
maximum
deviation from
the median.
0.3
UI
Jitter is defined as the measurement variation of the
crossing points (VRX-DIFFp-p = 0 V) in relation to a
recovered TX UI. A recovered TX UI is calculated over
3500 consecutive unit intervals of sample data. Jitter
is measured using all edges of the 250 consecutive UI
in the center of the 3500 UI used for calculating the TX
UI. See Notes 2, 3, and 7
VTX-DIFF = 0 mV
(D+ D– Crossing Point)
[De-Emphasized Bit]
0.07 UI = UI – 0.3 UI (JTX-TOTAL-MAX)
566 mV (3 dB ) >=
VTX-DIFFp-p-MIN >= 505 mV (4 dB )
[Transition Bit]
VTX-DIFFp-p-MIN = 800 mV
VRX-DIFF = 0 mV
(D+ D– Crossing Point)
[Transition Bit]
VTX-DIFFp-p-MIN = 800 mV
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