參數(shù)資料
型號(hào)： KMC8610VT1333JB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 6/96頁(yè)
文件大小： 0K
描述： IC HOST PROCESS 1333MHZ 783-PBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.333GHz
電壓： 1.025V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Pin Assignments and Reset States
Freescale Semiconductor
14
ASLEEP
cfg_core_speed
B26
—
OVDD
13
MSRCID0
cfg_mem_debug
Y20
—
BVDD
MDVAL
cfg_boot_vector
AC20
—
BVDD
Notes:
1. Multi-pin signals such as LDP[0:3] have their physical package pin numbers listed in order corresponding to the signal names.
2. Stub series terminated logic type pins.
3. All SSI signals are multiplexed with eLBC signals.
4. Low voltage transistor-transistor logic (LVTTL) type pins.
5. DIU_LD[23:16] = RED[7:0].
DIU_LD[15:8] = GREEN[7:0].
DIU_LD[7:0] = BLUE[7:0].
6. The pins for the SSI interface on the device are multiplexed with certain eLBC signals, which have the ability to operate at a
different voltage than the other standard I/O signals. If the device is configured such that the eLBC uses a different voltage
than standard I/O and an SSI port on the device is used, then level shifters are required on the SSI signals to ensure they
correctly interface to other devices on the board at the proper voltage.
7. This pin should be pulled to ground with a 100-
Ω resistor.
8. This pin should be pulled to ground with a 200-
Ω resistor.
9. These pins should be left floating.
10.This is a SerDes PLL/DLL digital test signal and is only for factory use.
11.This is a SerDes PLL/DLL analog test signal and is only for factory use.
12.This pin should be pulled down if the platform frequency is 400 MHz or below.
13.This pin should be pulled down if the core frequency is 800 MHz or below.
14.MSRCID[1:2], DIU_LD[5:6] and TRIG_OUT/READY should NOT be pulled down (or driven low) during reset.15. The pins in
this section are reset configuration pins. Each pin has a weak internal pull-up P-FET which is enabled only when the
processor is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k
Ω pull-down
resistor. However, if the signal is intended to be high after reset, and if there is any device on the net which might pull down
the value of the net at reset, then a pullup or active driver is needed.
16.These pins should be left floating.
17.Must be tied low if unused.
18.This output is actively driven during reset rather than being tri-stated during reset.
19.MDIC[0] should be connected to ground with an 18-
Ω resistor ± 1 Ω and MDIC[1] should be connected to GVDD with an 18-Ω
resistor ± 1
Ω. These pins are used for automatic calibration of the DDR IOs.
20.This pin is a reset configuration pin and appears again in the Reset Configuration Signals section of this table. See the Reset
Configuration Signals section of this table for config name and connection details.
21.Recommend a weak pull-up resistor (1–10 k
Ω) be placed from this pin to its power supply.
22.This multiplexed pin has input status in one mode and output in another.
23.This pin is a multiplexed signal for different functional blocks and appears more than once in this table.
24.For systems which boot from local bus (GPCM)-controlled flash, a pullup on LGPL4 is required.
25.This pin is open drain signal.
26.These are test signals for factory use only and must be pulled up (100
Ω to 1 kΩ) to OVDD for normal machine operation.
27.These JTAG pins have weak internal pull-up P-FETs that are always enabled.
28.These pins are connected to the power/ground planes internally and may be used by the core power supply to improve
tracking and regulation.
Table 1. Signal Reference by Functional Block (continued)
Name1
Package Pin Number
Pin Type
Power Supply
Notes
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