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參數(shù)資料
| 型號(hào)： | KMC8610VT1066JB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 76/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC HOST PROCESS 1066MHZ 783-PBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC86xx |
| 處理器類型： | 32-位 MPC86xx PowerPC |
| 速度： | 1.066GHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Hardware Design Considerations
Freescale Semiconductor
78
SerDes—Receiver lanes configured for PCI Express are allowed to be disconnected (as would occur when a PCI
Express slot is connected but not populated). Directions for terminating the SerDes signals is discussed in Section 3.10,
3.6
Pull-Up and Pull-Down Resistor Requirements
The MPC8610 requires weak pull-up resistors (2–10 k
Ω is recommended) on open drain type pins including I2C pins and PIC
interrupt pins.
Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 53.
Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most
have asynchronous behavior and spurious assertion will give unpredictable results.
Refer to the PCI 2.2 specification for all pull-ups required for PCI.
The following pins must not be pulled down during power-on reset: DIU_LD[5:6], MSRCID[1:2], HRESET_REQ, and
TRIG_OUT/READY.
The following are factory test pins and require strong pull up resistors (100
Ω – 1 kΩ) to OVDD: LSSD_MODE,
TEST_MODE[0:3].
The following pins require weak pull-up resistors (2–10 k
Ω) to their specific power supplies: LCS[0:4], LCS[5]/DMA_DREQ2,
LCS[6]/DMA_DACK[2], LCS[7]/DMA_DDONE[2], IRQ_OUT, IIC1_SDA, IIC1_SCL, IIC2_SDA, IIC2_SCL, and
CKSTP_OUT.
The following pins should be pulled to ground with a 100-
Ω resistor: SD1_IMP_CAL_TX, SD2_IMP_CAL_TX. The following
pins should be pulled to ground with a 200-
Ω resistor: SD1_IMP_CAL_RX, SD2_IMP_CAL_RX.
When the platform frequency is 400 MHz, cfg_platform_freq must be pulled down at reset. Also, cfg_dram_type[0 or 1] must
be valid at power-up even before HRESET assertion.
For other pin pull-up or pull-down recommendations of signals, see Section 1, “Pin Assignments and Reset States.”
3.7
Output Buffer DC Impedance
The MPC8610 drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull
single-ended driver type (open drain for I
2C).
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then, the
value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 51). The output impedance is the average of two
components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and
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