參數(shù)資料
型號: KMC8610VT1066JB
廠商: Freescale Semiconductor
文件頁數(shù): 31/96頁
文件大小: 0K
描述: IC HOST PROCESS 1066MHZ 783-PBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC86xx
處理器類型: 32-位 MPC86xx PowerPC
速度: 1.066GHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
Electrical Characteristics
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
37
2.8.2
DIU AC Timing Specifications
Figure 12 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and the data. All
parameters shown in the diagram are programmable. This timing diagram corresponds to positive polarity of the
DIU_CLK_OUT signal and active-high polarity of the DIU_HSYNC, DIU_VSYNC, and DIU_DE signals. By default, all
control signals and the display data are generated at the rising edge of the internal pixel clock, and the DIU_CLK_OUT output
to drive the panel has the same polarity with the internal pixel clock. User can select the polarity of the DIU_HSYNC and
DIU_VSYNC signal (via the SYN_POL register), whether active-high or active-low, the default is active-high. The DIU_DE
signal is always active-high.
Figure 12. TFT DIU/LCD Interface Timing Diagram—Horizontal Sync Pulse
Low-level output voltage (OVDD = min, IOL = 100 μA)
VOL
—0.2
V
Note:
1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 2 and Table 3.
Table 27. DIU DC Electrical Characteristics (continued)
Parameter
Symbol
Min
Max
Unit
1
23
DELTA_X
tPWH
tBPH
tSW
tFPH
DIU_CLK_OUT
DIU_LD
DIU_HSYNC
DIU_DE
tPCP
1
Invalid Data
Start of Line
tHSP
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