參數(shù)資料
型號: KM68S4000C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 512Kx8 Bit Low Power and Low Voltage CMOS Static RAM(512K x 8位低功耗和低電壓CMOS 靜態(tài) RAM)
中文描述: 512Kx8位低功耗和低電壓的CMOS靜態(tài)RAM(為512k × 8位低功耗和低電壓的CMOS靜態(tài)RAM)的
文件頁數(shù): 2/9頁
文件大?。?/td> 143K
代理商: KM68S4000C
KM68S4000C Family
Preliminary
CMOS SRAM
Revision 0.0
June 1998
2
512K
×
8 bit Low Power and Low Voltage CMOS Static RAM
GENERAL DESCRIPTION
The KM68S4000C families are fabricated by SAMSUNG
s
advanced CMOS process technology. The families support
industrial operating temperature range and have various
package type for user flexibility of system design. The fami-
lies also support low data retention voltage for battery back-
up operation with low data retention current.
FEATURES
Process Technology : TFT
Organization : 512K
×
8
Power Supply Voltage
KM68S4000C Family : 2.3~2.7V
Low Data Retention Voltage : 2V(Min)
Three state output and TTL Compatible
Package Type : 32-TSOP2-400F/R
32-TSOP1-0820F, 32-TSOP1-0813.4F
PIN DESCRIPTION
Name
Function
Name
Function
A
0
~A
18
Address Inputs
Vcc
Power
WE
Write Enable Input
Vss
Ground
CS
Chip Select Input
I/O
1
~I/O
8
Data Inputs/Outputs
OE
Output Enable Input
PRODUCT FAMILY
1. The paramerter is measured with 30pF test load.
Product Family
Operating Temperature
Vcc Range
Speed(ns)
Power Dissipation
PKG Type
Standby
(I
SB1
, Max)
Operating
(I
CC2
, Max)
KM68S4000CLI-L
Industrial(-40~85
°
C)
2.3~2.7V
100*/120
15
μ
A
16mA
32-TSOP2-F/R
32-TSOP1-F
32-sTSOP1-F
FUNCTIONAL BLOCK DIAGRAM
(Forward)
32-TSOP2
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-TSOP2
(Reverse)
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A18
A18
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
A15
Precharge circuit.
Memory array
1024 rows
512
×
8 columns
I/O Circuit
Column select
Clk gen.
Row
select
A2 A3 A8 A9 A10
A13
A11
A0
A1
A4
A5
A6
A7
A14
CS
WE
I/O
1
Data
cont
Data
cont
OE
I/O
8
A12
A16
A18
A11
A9
A8
A13
WE
A17
A15
VCC
A16
A14
A7
A6
A5
A4
OE
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
32-TSOP1
32-
S
TSOP1
(Forward)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A17
Control
logic
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