參數(shù)資料
型號: KM44S4020CT
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 2M x 4Bit x 2 Banks Synchronous DRAM(2M x 4位 x 2組同步動態(tài)RAM)
中文描述: 2米x 4位× 2銀行同步DRAM(2米× 4位× 2組同步動態(tài)RAM)的
文件頁數(shù): 42/44頁
文件大小: 604K
代理商: KM44S4020CT
TIMING DIAGRAM - I
CMOS SDRAM
ELECTRONICS
REV. 4 Nov. '97
0
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Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
Precharge
Power-down
Entry
: Don't care
*Note :
1. Both banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + tss prior to Row active command.
3. Can not violate minimum refresh specification. (64ms)
*Note 1
Precharge
tSS
*Note 2
BA
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
A
10
/AP
tSS
tSS
ó
ó
ó
ó
ó
ó
ó
ó
ó
Ra
ó
ó
Ca
ó
ó
Ra
ó
ó
Qa0
Qa1
Qa2
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
Row Active
Precharge
Power-down
Exit
Active
Power-down
Entry
Active
Power-down
Exit
Read
tSHZ
*Note 3
ó
*Note 2
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