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參數(shù)資料
| 型號： | KL5KUSB201 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | USB2.0 Compliant Transceiver Chip |
| 中文描述： | USB2.0標準收發(fā)器芯片 |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 183K |
| 代理商： | KL5KUSB201 |
Kawasaki USB device
KL5KUSB201
Datasheet (digest)
rev 1.1E page
6/21
Copyright 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
generation (optional), bit stuffed and NRZI encoded. Packet is transmitted onto
USB bus with SYNC and EOP attached
5. USB Bus status is delivered for outside SIE to monitor it
6. Function is controlled by Input Signals
7. Function defined by UTMI Specification is supported
8. Stand-alone Test packet generation for High Speed Signal Quality
1.2 KL5KUSB201 Product Feature
KL5KUSB201 Product Feature is shown below.
Table 1-2 KL5KUSB201 Product Feature
No
Item
1
Process
2
Package
3
Input Clock Frequency
4
Internal Clock Frequency
5
Output Clock Frequency
(CKOUT)
6
USB port
Feature
0.18um CMOS
LQFP 80 pin plastic package
48MHz
480MHz
、
48MHz and other
30MHz
1 port
(USB pin is separated for HS and FS)
16bit
3.3
±
0.3V
、
1.8
±
0.15V
typical 50mA
typical 90mA
1uA
0
～
70°C
7
8
9
10
11
12
Parallel Data width (SIE_DAT)
Power voltage
Operation Current in FS
Operation Current in HS
Operation Current at suspend
Ambient Temperature
Please contact to our sales and marketing person to request samples, datasheet,
USB201 IP and / or HS_SIE included ASCP planning.
2. Chip Architecture
Internal Architecture of KL5KUSB201 is shown in figure 2. The LSI consists of 6 major
blocks as follows.
FrontEnd block
transmits and receives USB signals.
HS DLL
block
is used to re-clock High Speed signals with internal 480MHz clock.
EBUF block
is for buffering High Speed signals.
Shared Logic block
includes such function as
NRZI decode, bit un-stuffing, CRC check, serial to parallel conversion for both High
Speed and Full Speed USB signals.
SIE_IF block
interfaces with SIE bus signals. For
Full Speed operation,
DPLL block
is used to re-clock the Full Speed signals with
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