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| 型號(hào)： | KAI-1020-ABB-JB-AE |
| 廠商： | KODAK IMAGE SENSOR SOLUTIONS |
| 元件分類(lèi)： | CCD Image Sensor |
| 英文描述： | IMAGE SENSOR-CCD, 1000(H) X 1000(V) PIXEL, 500mV, SQUARE, THROUGH HOLE MOUNT |
| 封裝： | PGA-68 |
| 文件頁(yè)數(shù)： | 30/72頁(yè) |
| 文件大小： | 3212K |
| 代理商： | KAI-1020-ABB-JB-AE |
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CORRELATED DOUBLE SAMPLING (CDS)
φR
φSA
φSB
φT
VOUTA
VOUTB
HCCD
vref
C
SA
C
SB
C
TB
output
C
TA
VDD
Correlated double sampling is a method of measuring
the amount of charge in each pixel. The electrons in the
last pixel of the HCCD are transferred onto a very small
sensing capacitor, C, on the falling edge of φH2S. The
voltage on C will change by about 20 μV for each electron
that was in the HCCD. The process of measuring the
amount of charge begins by resetting the value of C to an
internally generated reference voltage, vref. A short
pulse on φR at the rising edge of φH2S will reset C. After
C has been reset, its voltage is sampled and stored on
CSA by a short pulse on switch φSA. Then on the falling
edge of φH2S, electrons are transferred onto the
capacitor, C. The new voltage on C is sampled and stored
on CSB by a short pulse on switch φSB. These two
sampled voltages are then transferred to capacitors CTA
and CTB by a short pulse on φT. φT and φR generally occur
at the same time. An external operational amplifier is
used to subtract the two voltages on VOUTA and VOUTB.
The output of the op-amp will be proportional to the
number of electrons contained in one pixel. Note that it
takes one entire pixel clock cycle for the value of the
pixel to appear on VOUTA and VOUTB. The A and B
outputs of the CDS circuit will be in the range of 7 to 11
volts.
CDS Timing Edge Alignment
1. The edge alignments of the CDS timing pulses
φSA, φSB, φT, and φR are critical to proper
operation of the CDS circuit.
2. The falling edge of φR must not overlap the
rising edge of φSA
3. The falling edge of φSA must come at the same
time or before the falling edge of φH2
4. The rising edge of φSB must come after the
falling edge of φH2
5. The falling edge of φSB must come before the
rising edge of φR
6. The rising edge of φR may come before the rising
edge of φH2
7. φT should always be driven by the same timing
signal as φR
8. The pulse widths should be set such that φR,
φSA, and φSB are 1/3 of T
P
Eastman Kodak Company, 2007
www.kodak.com/go/imagers
Revision 5.0 MTD/PS-0205 p36
相關(guān)PDF資料 |
PDF描述 |
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| KAI-16000-AAA-JD-AE | IMAGE SENSOR-CCD, 4872(H) X 3248(V) PIXEL, RECTANGULAR, THROUGH HOLE MOUNT |
| KAI-2001-AAA-CF-BA | IMAGE SENSOR-CCD, 1600(H) X 1200(V) PIXEL, RECTANGULAR, THROUGH HOLE MOUNT |
| KAS1104E | SLIDE DIP SWITCH-4SWITCHES, SPST, LATCHED,THROUGH HOLE-STRAIGHT |
| KBL06 | 4 A, 600 V, SILICON, BRIDGE RECTIFIER DIODE |
| KBP04G | 1.5 A, 400 V, SILICON, BRIDGE RECTIFIER DIODE |
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