參數(shù)資料
型號: KAD5512HP-12Q72
廠商: Intersil
文件頁數(shù): 1/34頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 125MSPS SGL 72-QFN
產品培訓模塊: High-Speed Analog-to-Digital Converters
標準包裝: 1
系列: FemtoCharge™
位數(shù): 12
采樣率(每秒): 125M
數(shù)據(jù)接口: 串行,SPI?
轉換器數(shù)目: 1
功率耗散(最大): 376mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 72-VFQFN 裸露焊盤
供應商設備封裝: 72-QFN(10x10)
包裝: 托盤
輸入數(shù)目和類型: 1 個差分,單極
1
FN6808.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
KAD5512HP
High Performance 12-Bit,
250/210/170/125MSPS ADC
The KAD5512HP is the high-performance member of the
KAD5512 family of 12-bit analog-to-digital converters.
Designed with Intersil’s proprietary FemtoCharge
technology on a standard CMOS process, the family supports
sampling rates of up to 250MSPS. The KAD5512HP is part of
a pin-compatible portfolio of 10, 12 and 14-bit A/Ds with
sample rates ranging from 125MSPS to 500MSPS.
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters
such as gain and offset.
Digital output data is presented in selectable LVDS or CMOS
formats. The KAD5512HP is available in 72- and 48-contact
QFN packages with an exposed paddle. Operating from a
1.8V supply, performance is specified over the full industrial
temperature range (-40°C to +85°C).
Key Specifications
SNR = 68.2dBFS for fIN = 105MHz (-1dBFS)
SFDR = 81.1dBc for fIN = 105MHz (-1dBFS)
Power Consumption
- 429/345mW @ 250/125MSPS (SDR Mode)
- 390/309mW @ 250/125MSPS (DDR Mode)
Features
Pin-Compatible with the KAD5512P Family, Offering
2.2dB Higher SNR
Programmable Gain, Offset and Skew control
950MHz Analog Input Bandwidth
60fs Clock Jitter
Over-Range Indicator
Selectable Clock Divider:
÷1, ÷2 or ÷4
Clock Phase Selection
Nap and Sleep Modes
Two’s Complement, Gray Code or Binary Data Format
DDR LVDS-Compatible or LVCMOS Outputs
Programmable Built-in Test Patterns
Single-Supply 1.8V Operation
Pb-Free (RoHS Compliant)
Applications
Power Amplifier Linearization
Radar and Satellite Antenna Array Processing
Broadband Communications
High-Performance Data Acquisition
Communications Test Equipment
WiMAX and Microwave Receivers
DIGITAL
ERROR
CORRECTION
LVDS/CMOS
DRIVERS
1.25V
CLOCK
GENERATION
SHA
VINP
VINN
12-BIT
250 MSPS
ADC
CLKP
CLKN
SPI
CONTROL
CS
B
SC
LK
SDI
O
VSS
A
VSS
AV
D
CLKOUTP
CLKOUTN
D[11:0]P
D[11:0]N
ORP
ORN
OUTFMT
OUTMODE
OV
DD
SD
O
NA
PS
LP
CL
K
D
IV
+
VCM
Pin-Compatible Family
MODEL
RESOLUTION
SPEED
(MSPS)
KAD5514P-25
14
250
KAD5514P-21
14
210
KAD5514P-17
14
170
KAD5514P-12
14
125
KAD5512P-50
12
500
KAD5512P-25,
KAD5512HP-25
12
250
KAD5512P-21,
KAD5512HP-21
12
210
KAD5512P-17,
KAD5512HP-17
12
170
KAD5512P-12,
KAD5512HP-12
12
125
KAD5510P-50
10
500
Data Sheet
October 1, 2009
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