17 FN7693.2 May 2, 2011 This dual transformer scheme is used to improve common-mode rejection, which keeps the common-mode level of th" />
參數(shù)資料
型號(hào)： KAD5510P-12Q48
廠商： Intersil
文件頁(yè)數(shù)： 9/31頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT CMOS 125MSPS 48QFN
標(biāo)準(zhǔn)包裝： 100
系列： FemtoCharge™
位數(shù)： 10
采樣率（每秒）： 125M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 205mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 48-QFN（7x7）
包裝： 托盤(pán)
輸入數(shù)目和類(lèi)型： *
KAD5510P
17
FN7693.2
May 2, 2011
This dual transformer scheme is used to improve common-mode
rejection, which keeps the common-mode level of the input matched to
VCM. The value of the shunt resistor should be determined based on the
desired load impedance. The differential input resistance of the
KAD5510P is 1000
Ω.
The SHA design uses a switched capacitor input stage
(see Figure 42 on page 27), which creates current spikes when
the sampling capacitance is reconnected to the input voltage.
This causes a disturbance at the input which must settle before
the next sampling point. Lower source impedance will result in
faster settling and improved performance. Therefore a 1:1
transformer and low shunt resistance are recommended for
optimal performance.
A differential amplifier, as shown in Figure 29, can be used in
applications that require DC-coupling. In this configuration, the
amplifier will typically dominate the achievable SNR and
distortion performance.
The current spikes from the SHA will try to force the analog input
pins toward ground. In cases where the input pins are biased with
more than 50 ohms in series from VCM care must be taken to
make sure the input common mode range is not violated. The
provided ICM value (250A/MHz * 250MHz = 625A at
250MSPS) may be used to calculate the expected voltage drop
across any series resistance.
VCM Output
The VCM output is buffered with a series output impedance of
20. It can easily drive a typical ADC driver’s 10k common
mode control pin. If an external buffer is not used the voltage
drop across the internal 20 impedance must be considered
when calculating the expected DC bias voltage at the analog
input pins.
Clock Input
The clock input circuit is a differential pair (see Figure 43).
Driving these inputs with a high level (up to 1.8VP-P on each
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels.
The recommended drive circuit is shown in Figure 30. A duty
cycle range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may impact
SNR performance. The clock inputs are internally self-biased to
AVDD/2 to facilitate AC coupling.
A selectable 2x frequency divider is provided in series with the
clock input. The divider can be used in the 2x mode with a
sample clock equal to twice the desired sample rate. This allows
the use of the Phase Slip feature, which enables synchronization
of multiple ADCs.
The clock divider can be controlled through the SPI port. Details on this
A delay-locked loop (DLL) generates internal clock signals for
various stages within the charge pipeline. If the frequency of the
input clock changes, the DLL may take up to 52s to regain lock
at 250MSPS. The lock time is inversely proportional to the
sample rate.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter (tJ) and SNR is shown in Equation 1 and is
illustrated in Figure 31.
FIGURE 27. TRANSFORMER INPUT FOR GENERAL PURPOSE
APPLICATIONS
ADT1-1WT
0.1F
KAD5512P
VCM
ADT1-1WT
1000pF
FIGURE 28. TRANSMISSION-LINE TRANSFORMER INPUT FOR
HIGH IF APPLICATIONS
ADTL1-12
0.1F
KAD5512P
VCM
ADTL1-12
1000pF
KAD5512P
VCM
0.1F
0.22F
69.8
49.9
100
348
CM
217
25
69.8
FIGURE 29. DIFFERENTIAL AMPLIFIER INPUT
Ω
FIGURE 30. RECOMMENDED CLOCK DRIVE
TC4-1W
200pF
200O
200pF
CLKP
CLKN
1000pF
Ω
SNR
20 log10
1
2
πfINtJ
-------------------
=
(EQ. 1)
相關(guān)PDF資料
PDF描述
MAX11604EEE+ IC ADC SERIAL 8BIT 12CH 16-QSOP
MAX11638EEE+ IC ADC 8BIT SRL 300KSPS 16QSOP
MAX11208AEUB+ IC ADC 19BIT SRL 120SPS 10UMAX
MAX11203EEE+ IC ADC 16BIT SPI/SRL 16QSOP
MAX11212AEUB+ IC ADC 18BIT SRL 120SPS 10UMAX
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KAD5510P-17Q48 功能描述:IC ADC 10BIT CMOS 170MSPS 48QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:FemtoCharge™ 產(chǎn)品培訓(xùn)模塊:Data Converter Basics 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):10 采樣率（每秒）:30M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:150mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類(lèi)型:1 個(gè)單端，單極 配用:296-10003-ND - EVAL MOD FOR THS1030296-10004-ND - EVAL MOD FOR THS1031
KAD5510P-21Q48 功能描述:IC ADC 10BIT CMOS 210MSPS 48QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:FemtoCharge™ 產(chǎn)品培訓(xùn)模塊:Data Converter Basics 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):10 采樣率（每秒）:30M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:150mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類(lèi)型:1 個(gè)單端，單極 配用:296-10003-ND - EVAL MOD FOR THS1030296-10004-ND - EVAL MOD FOR THS1031
KAD5510P-25Q48 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-BIT 250MSPS LW PW ADC PROG RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
KAD5510P-50 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:10-Bit, 500MSPS A/D Converter
KAD5510P-50_09 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:10-Bit, 500MSPS A/D Converter
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*