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參數(shù)資料
| 型號： | KAD5510P-12Q48 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 17/31頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT CMOS 125MSPS 48QFN |
| 標準包裝： | 100 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 205mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | * |
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KAD5510P
24
FN7693.2
May 2, 2011
ADDRESS 0X74: OUTPUT_MODE_B
ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default) or slow.
Internal clock signals are generated by a delay-locked loop (DLL),
which has a finite operating range. Table 11 shows the allowable
sample rate ranges for the slow and fast settings.
The output_mode_B and config_status registers are used in
conjunction to enable DDR mode and select the frequency range
of the DLL clock generator. The method of setting these options
is different from the other registers.
The procedure for setting output_mode_B is shown in Figure 41.
Read the contents of output_mode_B and config_status and XOR
them. Then XOR this result with the desired value for
output_mode_B and write that XOR result to the register.
Bit 4 DDR Enable
This bit sets the output mode to DDR or SDR.
This bit is set high by default enabling DDR outputs. Do not set
this bit low or invalid output data will result.
Device Test
The KAD5510 can produce preset or user defined patterns on the
digital outputs to facilitate in-site testing. A static word can be
placed on the output bus, or two different words can alternate. In
the alternate mode, the values defined as Word 1 and Word 2 (as
shown in Table 12) are set on the output bus on alternating clock
phases. The test mode is enabled asynchronously to the sample
clock, therefore several sample clock cycles may elapse before
the data is present on the output bus.
ADDRESS 0XC0: TEST_IO
Bits 7:6 User Test Mode
These bits set the test mode to static (0x00) or alternate
(0x01) mode. Other values are reserved.
The four LSBs in this register (Output Test Mode) determine the
test pattern in combination with registers 0xC2 through 0xC5.
Refer to Table 12.
ADDRESS 0XC2: USER_PATT1_LSB AND
ADDRESS 0XC3: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
ADDRESS 0XC4: USER_PATT2_LSB AND
ADDRESS 0XC5: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
48 Pin Package Notes
The KAD5510 is only available in a 48-pin package. While fully
compatible with other family members in the 48-pin package
there are some key differences from the 72-pin package. The 48
pin package option supports LVDS DDR only. A reduced set of pin
selectable functions are available in the 48 pin package due to
the reduced pinout; (OUTMODE, OUTFMT, and CLKDIV pins are
not available). Table 13 shows the default state for these
functions for the 48-pin package. Note that these functions are
available through the SPI, allowing a user to set these modes as
they desire, offering the same flexibility as the 72-pin family
members.
001
Two’s Complement
010
Gray Code
100
Offset Binary
TABLE 11. DLL RANGES
DLL RANGE
MIN
MAX
UNIT
Slow
40
100
MSPS
Fast
80
fS MAX
MSPS
TABLE 10. OUTPUT FORMAT CONTROL
(Continued)
VALUE
0x93[2:0]
OUTPUT FORMAT
FIGURE 41. SETTING OUTPUT_MODE_B REGISTER
READ
CONFIG_STATUS
0x75
READ
OUTPUT_MODE_B
0x74
DESIRED
VALUE
WRITE TO
0x74
TABLE 12. OUTPUT TEST MODES
VALUE
0xC0[3:0]
OUTPUT TEST MODE
WORD 1
WORD 2
0000
Off
0001
Midscale
0x8000
N/A
0010
Positive Full-Scale
0xFFFF
N/A
0011
Negative Full-Scale
0x0000
N/A
0100
Checkerboard
0xAAAA
0x5555
0101
Reserved
N/A
0110
Reserved
N/A
0111
One/Zero
0xFFFF
0x0000
1000
User Pattern
user_patt1
user_patt2
TABLE 13. 48 PIN SPI - ADDRESSABLE FUNCTIONS
FUNCTION
DESCRIPTION
DEFAULT STATE
CLKDIV
Clock Divider
Divide by 1
OUTMODE
Output Driver Mode
LVDS, 3mA (DDR)
OUTFMT
Data Coding
Two’s Complement
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