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參數(shù)資料
| 型號： | K7R161884B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx36 & 1Mx18 QDR II b4 SRAM |
| 中文描述： | 512Kx36 |
| 文件頁數(shù)： | 17/18頁 |
| 文件大?。?/td> | 418K |
| 代理商： | K7R161884B |
- 8 -
Rev 3.1
July. 2004
512Kx36 & 1Mx18 QDRTM II b4 SRAM
K7R163684B
K7R161884B
WRITE TRUTH TABLE(x18)
Notes: 1. X means "Don
′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (
↑ ).
3. Assumes a WRITE cycle was initiated.
4. This table illustates operation for x18 devices.
K
BW0
BW1
OPERATION
↑
L
WRITE ALL BYTEs ( K
↑ )
↑
L
WRITE ALL BYTEs ( K
↑ )
↑
L
H
WRITE BYTE 0 ( K
↑ )
↑
L
H
WRITE BYTE 0 ( K
↑ )
↑
H
L
WRITE BYTE 1 ( K
↑ )
↑
H
L
WRITE BYTE 1 ( K
↑ )
↑
H
WRITE NOTHING ( K
↑ )
↑
H
WRITE NOTHING ( K
↑ )
WRITE TRUTH TABLE(x36)
Notes: 1. X means "Don
′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (
↑ ).
3. Assumes a WRITE cycle was initiated.
K
BW0
BW1
BW2
BW3
OPERATION
↑
LLLL
WRITE ALL BYTEs ( K
↑ )
↑
LLLL
WRITE ALL BYTEs ( K
↑ )
↑
L
H
WRITE BYTE 0 ( K
↑ )
↑
L
H
WRITE BYTE 0 ( K
↑ )
↑
H
L
H
WRITE BYTE 1 ( K
↑ )
↑
H
L
H
WRITE BYTE 1 ( K
↑ )
↑
H
L
WRITE BYTE 2 and BYTE 3 ( K
↑ )
↑
H
L
WRITE BYTE 2 and BYTE 3 ( K
↑ )
↑
HHHH
WRITE NOTHING ( K
↑ )
↑
HHHH
WRITE NOTHING ( K
↑ )
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
Notes: 1. X means "Don
′t Care".
2. The rising edge of clock is symbolized by (
↑ ).
3. Before enter into clock stop status, all pending read and write operations will be completed.
4. This signal was HIGH on previous K clock rising edge. Initating consecutive READ or WRITE operations on consecutive K clock rising edges
is not permitted. The device will ignore the second request.
5. If this signal was LOW to inititate the previous cycle, this signal becomes a don
′t care for this operation however it is strongly recommended
that this signal is brought HIGH as shown in the truth table.
K
R
W
D
Q
OPERATION
D(A1)
D(A2)
D(A3)
D(A4)
Q(A1)
Q(A2)
Q(A3)
Q(A4)
Stopped
X
Previous
state
Previous
state
Previous
state
Previous
state
Previous
state
Previous
state
Previous
state
Previous
state
Clock Stop
↑
H
X
High-Z
No Operation
↑
L4
XX
X
DOUT
at C(t+1)
DOUT
at C(t+2)
DOUT
at C(t+2)
DOUT
at C(t+3)
Read
↑
H5
L4
Din
at K(t+1)
Din
at K(t+1)
Din
at K(t+2)
Din
at K(t+2)
X
XXX
Write
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PDF描述 |
|---|---|
| K7R163684B | 512Kx36 & 1Mx18 QDR II b4 SRAM |
| K7R323682 | 1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM |
| K971 | 85.05 mm2, COPPER ALLOY, TIN FINISH, RING TERMINAL |
| K972 | 85.05 mm2, COPPER ALLOY, TIN FINISH, RING TERMINAL |
| K973 | 85.05 mm2, COPPER ALLOY, TIN FINISH, RING TERMINAL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7R161884B-FC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDR II b4 SRAM |
| K7R161884B-FC20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDR II b4 SRAM |
| K7R161884B-FC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDR II b4 SRAM |
| K7R161884B-FC30 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDR II b4 SRAM |
| K7R163682B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 & 2Mx9 QDRTM II b2 SRAM |
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