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參數(shù)資料
| 型號： | JZ48F4L0QBY |
| 廠商： | Intel Corp. |
| 英文描述： | StrataFlash Wireless Memory |
| 中文描述： | 無線的StrataFlash存儲器 |
| 文件頁數(shù)： | 100/106頁 |
| 文件大?。?/td> | 1272K |
| 代理商： | JZ48F4L0QBY |
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Intel StrataFlash Wireless Memory (L18)
April 2005
100
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet
Table 29.
Partition Region 1 Information
Offset
(1)
P = 10Ah
Bottom
(P+24)h
(P+25)h
(P+26)h
See table below
Address
Len
Bot
2
12E:
12F:
1
130:
Description
Top
(P+24)h Number of identical partitions within the partition region
(P+25)h
(P+26)h
Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Types of erase block regions in this Partition Region.
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
(Optional flash features and commands)
Top
12E:
12F:
130:
(P+27)h
(P+27)h
1
131:
131:
(P+28)h
(P+28)h
1
132:
132:
(P+29)h
(P+29)h
1
133:
133:
(P+2A)h
(P+2B)h
(P+2C)h
(P+2D)h
(P+2E)h
(P+2F)h
(P+30)h
(P+2A)h Partition Region 1 Erase Block Type 1 Information
(P+2B)h
bits 0–15 = y, y+1 = number of identical-size erase blocks
(P+2C)h
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(P+2D)h
(P+2E)h Partition 1 (Erase Block Type 1)
(P+2F)h Minimum block erase cycles x 1000
(P+30)h
Partition 1 (erase block Type 1) bits per cell; internal ECC
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
Partition 1 (erase block Type 1) page mode and synchronous
mode capabilities defined in Table 10.
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
4
134:
135:
136:
137:
138:
139:
13A:
134:
135:
136:
137:
138:
139:
13A:
2
1
(P+31)h
(P+31)h
1
13B:
13B:
(P+32)h
(P+33)h
(P+34)h
(P+35)h
(P+36)h
(P+37)h
(P+38)h
Partition Region 1 Erase Block Type 2 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(bottom parameter device only)
Partition 1 (Erase block Type 2)
Minimum block erase cycles x 1000
Partition 1 (Erase block Type 2) bits per cell
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
Partition 1 (Erase block Type 2) pagemode and synchronous
mode capabilities defined in Table 10
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
4
13C:
13D:
13E:
13F:
140:
141:
142:
2
1
(P+39)h
1
143:
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