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參數(shù)資料
| 型號(hào)： | IXDP610 |
| 廠商： | IXYS Corporation |
| 英文描述： | Bus Compatible Digital PWM Controller, IXDP 610 |
| 中文描述： | 總線兼容數(shù)字PWM控制器，IXDP 610 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 181K |
| 代理商： | IXDP610 |
2001 IXYS/DEI All rights reserved
2
IXDP 610
Symbol
Definition
Operating Range
Maximum Ratings
min.
max.
V
CC
T
A
Supply voltage
Operating free air temperature
4.5
-40
5.5
85
V
°
C
Symbol
Definition/Condition
Characteristic Values
(Over operating range, unless otherwise specified)
min.
typ.
max.
V
IH(CMOS)
V
IL(CMOS)
V
H
V
OH
Input High Voltage
ODIS
3.8
V
CC
+0.3V
1.2
Input Low Voltage
ODIS
-0.3
V
Input Hysteresis
ODIS
0.3
0.5
V
Output High Voltage OUT1 I
OH
= -20 mA
2.4
V
OUT2
V
OL
Output Low Voltage
OUT1 I
OL
= 20 mA
OUT2
0.4
V
V
IH(TTL)
Input High Voltage
All Inputs
Except ODIS
2.0
V
CC
+0.3V
V
IL(TTL)
Input Low Voltage
All Inputs
Except ODIS
-0.3
0.8
V
I
LI
Input Leakage
Current
All Inputs
0 < V
I
< V
CC
f
CLK
= 5 MHz
V
IH
= V
CC
or 0
-10
-0.1
10
μ
A
I
CC
Power Supply
Current
3.5
10
mA
Symbol
Definition/Condition
Characteristic Values
(T
A
= 25
°
C, V
CC
= 5 V
±
10 %, C1 = 50 pF)
No. see
Fig. 3-6
-40...85
°
C
min.
typ.
max.
1
t
AVWL
SEL Stable to WR Low
5
ns
2
t
WHAX
SEL Stable after WR High
10
ns
3
t
SLWL
CS Low to WR Low
5
ns
4
t
WHSH
CS High after WR High
5
ns
5
t
WLWH
WR Pulse Width
8
20
ns
6
t
DVWH
Data Valid to WR High
5
ns
7
t
WHDX
Data Held after WR High
10
20
ns
8
f
CLK
Clock Frequency
50
*
0
50
*
MHz
9
t
CLCH
t
CHCL
Clock Pulse Duration Low
12.5
12.5
12.5
12.5
ns
ns
High
10 t
CHOV
CLK to Output when
Writing to PW latch
5+T
CLK
**
5
5+T
CLK
ns
11 t
ODLOL
ODIS Low to Output Low
20
50
ns
12 t
WHOL
WR High to Output Low
When Writing Stop to the
Control latch
30
60
ns
13 t
RLRH
RST Low Time
50
ns
*
** T
clk
= 1/f
clk
Output will change 1 rising CLOCK edge +5ns after WR (see Fig. 6)
Numbers in the Fig. 3 to 6 corres-
ponding to the time values on the
bottom left of this page.
Fig. 3
Write operation timing diagram
Fig. 4
Output disable to outputs off
timing
Fig. 5
Stop to outputs off timing
Fig. 6
CLOCK to output when writing
to PW latch
OUT 1 or OUT2
WR
OUT1
OUT2
1
8
10
<5ns
9
9
2
3
CLK
WR
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IXDP610PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| IXDP610PI | 功能描述:電壓模式 PWM 控制器 Bus Compatibl Digitl PWM Controller RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:1 拓?fù)浣Y(jié)構(gòu):Buck 輸出電壓:34 V 輸出電流: 開(kāi)關(guān)頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel |
| IXDP610PM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| IXDP630 | 制造商:IXYS 制造商全稱:IXYS Corporation 功能描述:Inverter Interface and Digital Deadtime Generator for 3-Phase PWM Controls |
| IXDP630PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Delay Circuit |
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