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參數(shù)資料
| 型號： | ISPPAC-CLK5610V-01T48C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Spot Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:160mA; Supply Voltage:30VDC; Wavelength:470nm |
| 中文描述： | 5600 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數(shù)： | 32/47頁 |
| 文件大?。?/td> | 871K |
| 代理商： | ISPPAC-CLK5610V-01T48C |
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Lattice Semiconductor
ispClock5600 Family Data Sheet
32
When the ispClock5600 begins operating from initial power-on, the VCO starts running at a very low frequency
(<100 MHz) which gradually increases as it approaches a locked condition. To prevent invalid outputs from being
applied to the rest of the system, it is recommended that either the SGATE, OEX, or OEY pins be used to control
the outputs based on the status of the LOCK pin. Holding the SGATE pin LOW during power-up will result in the
BANK outputs being asserted HIGH or LOW (depending on inversion status) until SGATE is brought HIGH. Assert-
ing OEX or OEY high will result in the BANK outputs being held in a high-impedance state until the OEX or OEY
pin is pulled LOW. One should not use the GOE pin to control the outputs in anticipation of LOCK status, as holding
GOE HIGH also disables internal feedback and will prevent the device from ever achieving lock.
Software-Based Design Environment
Designers can con
fi
gure the ispClock5600 using Lattice’s PAC-Designer software, an easy to use, Microsoft Windows
compatible program. Circuit designs are entered graphically and then veri
fi
ed, all within the PAC-Designer environ-
ment. Full device programming is supported using PC parallel port I/O operations and a download cable connected to
the serial programming interface pins of the ispClock5600. A library of con
fi
gurations is included with basic solutions
and examples of advanced circuit techniques are available on the Lattice web site at www.latticesemi.com. In addi-
tion, comprehensive on-line and printed documentation is provided that covers all aspects of PAC-Designer operation.
The PAC-Designer schematic window, shown in Figure 28 provides access to all con
fi
gurable ispClock5600 elements
via its graphical user interface. All analog input and output pins are represented. Static or non-con
fi
gurable pins such
as power, ground and the serial digital interface are omitted for clarity. Any element in the schematic window can be
accessed via mouse operations as well as menu commands. When completed, con
fi
gurations can be saved and
downloaded to devices.
Figure 28. PAC-Designer Design Entry Screen
In-System Programming
The ispClock5600 is an In-System Programmable (ISP) device. This is accomplished by integrating all E
2
CMOS
con
fi
guration control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant serial JTAG
interface at normal logic levels. Once a device is programmed, all con
fi
guration information is stored on-chip, in
non-volatile E
2
CMOS memory cells. The speci
fi
cs of the IEEE 1149.1 serial interface and all ispClock5600 instruc-
tions are described in the JTAG interface section of this data sheet.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK5620V-01T48C | LED Area Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:525nm |
| ISPPAC-CLK5610V-01T48I | LED Area Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:525nm |
| ISPPAC-CLK5620V-01T48I | Linear Array Light; LED Color:Green; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:800mA; Supply Voltage:24VDC; Wavelength:530nm |
| ISPPAC-CLK5610V-01TN100C | LED On-Axis Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:100x100mm; Peak Reflow Compatible (260 C):No; Supply Current:500mA; Supply Voltage:24VDC; Wavelength:520nm |
| ISPPAC-CLK5620V-01TN100C | Spot Light; LED Color:Green; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:160mA; Supply Voltage:30VDC; Wavelength:530nm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC-CLK5610V-01T48I | 功能描述:時鐘驅(qū)動器及分配 PROGRAMMABLE ZERO DELAY CL GEN RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPAC-CLK5610V-01TN100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01TN100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01TN48C | 功能描述:時鐘驅(qū)動器及分配 PROGRAMMABLE ZERO DELAY CL GEN RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPAC-CLK5610V-01TN48I | 功能描述:時鐘驅(qū)動器及分配 PROGRAMMABLE ZERO DELAY CL GEN RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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