參數(shù)資料
型號(hào)： ISPPAC-CLK5610V-01T48C
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： 時(shí)鐘及定時(shí)
英文描述： Spot Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:160mA; Supply Voltage:30VDC; Wavelength:470nm
中文描述： 5600 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
封裝： TQFP-48
文件頁(yè)數(shù)： 23/47頁(yè)
文件大?。?/td> 871K
代理商： ISPPAC-CLK5610V-01T48C
Lattice Semiconductor
ispClock5600 Family Data Sheet
23
In the case where an output bank is unused, the associated VCCO pin may be either left
fl
oating or tied to ground
to reduce quiescent power consumption. We recommend, however, that all unused VCCO pins be tied to ground
where possible. All GND0 pins must be tied to ground, regardless of whether or not the associated bank is used.
Figure 19. ispClock5600 Output Driver and Skew Control
Each of the ispClock5600’s output driver banks can be con
fi
gured to support the following logic outputs:
LVTTL
LVCMOS (1.8V, 2.5V, 3.3V)
SSTL2
SSTL3
HSTL
LVDS
Differential LVPECL (3.3V)
To provide LVTTL, LVCMOS, SSTL2, SSTL3, and HSTL outputs, the CMOS output drivers in each bank are
enabled. These circuits provide logic outputs which swing from ground to the VCCO supply rail. The choice of
VCCO to be supplied to a given bank is determined by the logic standard to which that bank is con
fi
gured. Because
each pair of outputs has its own VCCO supply pin, each bank can be independently con
fi
gured to support a differ-
ent logic standard. Note that the two outputs associated with a bank must necessarily be con
fi
gured to the same
logic standard. The source impedance of each of the two outputs in each bank may be independently set over a
range of 40
to 70
in 5
steps. A low impedance option (
≈
20
) is also provided for cases where low source ter-
mination is desired on a given output.
Control of output slew rate is also provided in LVTTL, LVCMOS, SSTL2, SSTL3, and HSTL output modes. Four
output slew-rate settings are provided, as speci
fi
ed in the “Output Rise Times” and “Output Fall Times” tables in this
data sheet.
To provide LVDS and differential LVPECL outputs, a separate internal driver is used which provides the correct
LVDS or LVPECL logic levels when operating from a 3.3V VCCO. Because both LVDS and differential LVPECL
transmission lines are normally terminated with a single 100
resistor between the ‘+’ and ‘-’ signal lines at the far
OE
Control
From V-Dividers
Skew
Adjust
Skew
Adjust
BANKxA
BANKxB
Single-ended
‘A’ output Driver
Single-ended
‘B’ output Driver
Differential
(PECL/LVDS)
Driver
OE
Control
OE
Control
相關(guān)PDF資料
PDF描述
ISPPAC-CLK5620V-01T48C LED Area Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:525nm
ISPPAC-CLK5610V-01T48I LED Area Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:525nm
ISPPAC-CLK5620V-01T48I Linear Array Light; LED Color:Green; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:800mA; Supply Voltage:24VDC; Wavelength:530nm
ISPPAC-CLK5610V-01TN100C LED On-Axis Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:100x100mm; Peak Reflow Compatible (260 C):No; Supply Current:500mA; Supply Voltage:24VDC; Wavelength:520nm
ISPPAC-CLK5620V-01TN100C Spot Light; LED Color:Green; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:160mA; Supply Voltage:30VDC; Wavelength:530nm
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPAC-CLK5610V-01T48I 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 PROGRAMMABLE ZERO DELAY CL GEN RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPAC-CLK5610V-01TN100C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5610V-01TN100I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5610V-01TN48C 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 PROGRAMMABLE ZERO DELAY CL GEN RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPAC-CLK5610V-01TN48I 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 PROGRAMMABLE ZERO DELAY CL GEN RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
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