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參數(shù)資料
| 型號： | ISPPAC-CLK5520V-01TN100C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Linear Array Light; LED Color:Green; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:1.6A; Supply Voltage:24VDC; Wavelength:530nm |
| 中文描述： | 5500 SERIES, PLL BASED CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP100 |
| 封裝： | LEAD FREE, TQFP-100 |
| 文件頁數(shù)： | 34/43頁 |
| 文件大?。?/td> | 867K |
| 代理商： | ISPPAC-CLK5520V-01TN100C |
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Lattice Semiconductor
ispClock5500 Family Data Sheet
34
type and version code (Figure 30). Access to the Identi
fi
cation Register is immediately available, via a TAP data
scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this
instruction is de
fi
ned by Lattice as shown in Table 8.
Figure 30. ispClock5500 Family ID Codes
In addition to the four instructions described above, there are 20 unique instructions speci
fi
ed by Lattice for the
ispClock5520. These instructions are primarily used to interface to the various user registers and the E
2
CMOS non-
volatile memory. Additional instructions are used to control or monitor other features of the device, including bound-
ary scan operations. A brief description of each unique instruction is provided in detail below, and the bit codes are
found in Table 8.
PROGRAM_ENABLE
– This instruction enables the ispClock5500’s programming mode.
PROGRAM_DISABLE
– This instruction disables the ispClock5500’s programming mode.
BULK_ERASE
– This instruction will erase all E
2
CMOS bits in the device, including those the UES data and elec-
tronic security fuse (ESF). A bulk erase instruction must be issued before reprogramming a device. The device
must already be in programming mode for this instruction to execute.
ADDRESS_SHIFT
– This instruction shifts address data into the address register (10 bits) in preparation for either
a PROGRAM or VERIFY instruction.
DATA_SHIFT
– This instruction shifts data into or out of the data register (90 bits), and is used with both the PRO-
GRAM and VERIFY instructions.
PROGRAM
– This instruction programs the contents of the data register to the E
2
CMOS memory column pointed
to by the address register. The device must already be in programming mode for this instruction to execute.
PROG_INCR
– This instruction
fi
rst programs the contents of the data register into E
2
CMOS memory column
pointed to by the address register and then auto-increments the value of the address register. The device must
already be in programming mode for this instruction to execute.
PROGRAM_SECURITY
– This instruction programs the electronic security fuse (ESF). This prevents data other
than the ID code and UES strings from being read fro the device. The electronic security fuse may only be reset by
issuing a BULK_ERASE command. The device must already be in programming mode for this instruction to exe-
cute.
XXXX
/
0000 0001 0101 0010
/
0000 0100 001
/
1
MSB
LSB
Part Number
(16 bits)
0152h = ispClock5510
(3.3V version)
Version
(4 bits)
E
2
Configured
JEDEC Manufacturer
Identity Code for
Lattice Semiconductor
(11 bits)
Constant ‘1’
(1 bit)
per 1149.1-1990
XXXX
/
0000 0001 0101 0000
/
0000 0100 001
/
1
MSB
LSB
Part Number
(16 bits)
0150h = ispClock5520
(3.3V version)
Version
(4 bits)
E
2
Configured
JEDEC Manufacturer
Identity Code for
Lattice Semiconductor
(11 bits)
Constant ‘1’
(1 bit)
per 1149.1-1990
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK55xx | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5510V | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5510V-01T48C | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5510V-01T48I | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5520V-01T100C | LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:470nm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5520V-01TN100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5520V-01TN100I | 功能描述:時鐘驅(qū)動器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5520V-01TN100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPACCLK5520V-01TN48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPACCLK5520V-01TN48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
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