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參數(shù)資料
| 型號： | ISPPAC-CLK5520V-01T100I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:800mA; Supply Voltage:24VDC; Wavelength:470nm |
| 中文描述： | 5500 SERIES, PLL BASED CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 27/43頁 |
| 文件大?。?/td> | 867K |
| 代理商： | ISPPAC-CLK5520V-01T100I |
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Lattice Semiconductor
ispClock5500 Family Data Sheet
27
Figure 23. Additional Factor-of-2 Division in Coarse Mode
When one moves from
fi
ne skew mode to coarse skew mode with a given divider con
fi
guration, the VCO frequency
will attempt to double to compensate for the additional divide-by-2 stage. Because the f
VCO
range is not increased,
however, one must modify the V-divider settings to bring f
VCO
back into its speci
fi
ed operating range (320MHz to
640MHz). This can be accomplished by dividing all V-divider settings by two. All output frequencies will remain
unchanged from what they were in
fi
ne mode. One drawback of moving from
fi
ne skew mode into coarse skew
mode is that it may not be possible to maintain consistent output frequencies, as only those V-divider settings which
are multiples of four (in
fi
ne mode) may be divided by two. For example, a V-divider setting of 24 will divide down to
12, which is also a legal V-divider setting, whereas an initial setting of 26 would divide down to 13, which is not a
valid setting.
When one moves from coarse skew mode to
fi
ne skew mode, the extra divide-by-two factor is removed from
between the VCO and the V-divider bank, halving the VCO’s effective operating frequency. To compensate for this
change, all of the V-dividers must be doubled to move the VCO back into its speci
fi
ed operating range and maintain
consistent output frequencies. The only situation in which this may be a problem is when a V-divider initially in
coarse mode has a value greater than 32, as the corresponding
fi
ne skew mode setting would be greater than 64,
which is not supported.
Skew Matching and Accuracy
Understanding the various factors which relate to output skew is essential for realizing optimal skew performance in
the ispClock5500 family of devices.
In the case where two outputs are identically con
fi
gured, and driving identical loads, the maximum skew is de
fi
ned
by t
SKEW,
which is speci
fi
ed as a maximum of 50ps. In Figure 24 the Bank1A and BANK2A outputs show the skew
error between two matched outputs.
Figure 24. Skew Matching Error Sources
VCO
÷
2
V-dividers
Fine
Mode
Fout
Coarse
Mode
+/- t
SKEW
2ns +/- (t
SKEW
) +/- (t
SKERR
)
BANK1A
(skew setting = 0)
BANK2A
(skew setting=0)
BANK3A
(skew setting = 2ns)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK5520V-01TN100I | LED Area Light; LED Color:Infrared; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:150mA; Supply Voltage:24VDC; Wavelength:940nm |
| ISPPAC-CLK5510V-01TN48C | Backlight LED; Color:Infrared; Digit/Alpha Height:85mm; Forward Current:500mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:85x220mm; Peak Reflow Compatible (260 C):No |
| ISPPAC-CLK5510V-01TN48I | LED Area Light; Forward Current:300mA; Operating Temperature Range:0 C to +50 C; LED Color:Red; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA |
| ISPPAC-CLK5610V-01T100I | Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:1.6A; Supply Voltage:24VDC; Wavelength:470nm |
| ISPCLOCK5600 | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5520V-01T100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPACCLK5520V-01T48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPACCLK5520V-01T48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5520V-01TN100C | 功能描述:時鐘驅(qū)動器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5520V-01TN100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
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