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參數(shù)資料
| 型號： | ISPPAC-CLK5520V-01T100I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:800mA; Supply Voltage:24VDC; Wavelength:470nm |
| 中文描述： | 5500 SERIES, PLL BASED CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 22/43頁 |
| 文件大?。?/td> | 867K |
| 代理商： | ISPPAC-CLK5520V-01T100I |
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Lattice Semiconductor
ispClock5500 Family Data Sheet
22
Each of the ispClock5500’s output driver banks can be con
fi
gured to support the following logic outputs:
LVTTL
LVCMOS (1.8V, 2.5V, 3.3V)
SSTL2
SSTL3
HSTL
LVDS
Differential LVPECL (3.3V)
To provide LVTTL, LVCMOS, SSTL2, SSTL3, and HSTL outputs, the CMOS output drivers in each bank are
enabled. These circuits provide logic outputs which swing from ground to the VCCO supply rail. The choice of
VCCO to be supplied to a given bank is determined by the logic standard to which that bank is con
fi
gured. Because
each pair of outputs has its own VCCO supply pin, each bank can be independently con
fi
gured to support a differ-
ent logic standard. Note that the two outputs associated with a bank must necessarily be con
fi
gured to the same
logic standard. The source impedance of each of the two outputs in each bank may be independently set over a
range of 40
to 70
in 5
steps. A low impedance option (
≈
20
) is also provided for cases where low source ter-
mination is desired on a given output, such as when using HSTL output mode.
Control of output slew rate is also provided in LVTTL, LVCMOS, SSTL2, SSTL3, and HSTL output modes. Four
output slew-rate settings are provided, as speci
fi
ed in the “Output Rise Times” and “Output Fall Times” tables in this
data sheet.
To provide LVDS and differential LVPECL outputs, a separate driver is used which provides the correct LVDS or
LVPECL logic levels when operating from a 3.3V VCCO. Because both LVDS and differential LVPECL transmission
lines are normally terminated with a single 100
resistor between the ‘+’ and ‘-’ signal lines at the far end, the
ispClock5500’s internal termination resistors are not available in these modes. Also note that output slew-rate con-
trol is not available in LVDS or LVPECL mode, and that these drivers always operate at a
fi
xed slew-rate.
Polarity control (true/inverted) is available for all output drivers. In the case of single-ended output standards, the
polarity of each of the two output signals from each bank may be controlled independently. In the case of differen-
tial output standards, the polarity of the differential pair may be selected.
Suggested Usage
Figure 19 shows a typical con
fi
guration for the ispClock5500’s output driver when con
fi
gured to drive an LVTTL or
LVCMOS load. The ispClock5500’s output impedance should be set to match the characteristic impedance of the
transmission line being driven. The far end of the transmission line should be left open, with no termination resis-
tors.
Figure 19. Configuration for LVTTL/LVCMOS Output Modes
Figure 20 shows a typical con
fi
guration for the ispClock5500’s output driver when con
fi
gured to drive SSTL2,
SSTL3, or HSTL loads. The ispClock5500’s output impedance should be set to 40
for driving SSTL2 or SSTL3
Zo
Ro = Zo
ispClock5500
LVCMOS/LVTTL
Mode
LVCMOS/LVTTL
Receiver
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK5520V-01TN100I | LED Area Light; LED Color:Infrared; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:150mA; Supply Voltage:24VDC; Wavelength:940nm |
| ISPPAC-CLK5510V-01TN48C | Backlight LED; Color:Infrared; Digit/Alpha Height:85mm; Forward Current:500mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:85x220mm; Peak Reflow Compatible (260 C):No |
| ISPPAC-CLK5510V-01TN48I | LED Area Light; Forward Current:300mA; Operating Temperature Range:0 C to +50 C; LED Color:Red; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA |
| ISPPAC-CLK5610V-01T100I | Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:1.6A; Supply Voltage:24VDC; Wavelength:470nm |
| ISPCLOCK5600 | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5520V-01T100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPACCLK5520V-01T48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPACCLK5520V-01T48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5520V-01TN100C | 功能描述:時鐘驅(qū)動器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5520V-01TN100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
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