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參數(shù)資料
| 型號： | ISPPAC-CLK5510V-01TN48C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Backlight LED; Color:Infrared; Digit/Alpha Height:85mm; Forward Current:500mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:85x220mm; Peak Reflow Compatible (260 C):No |
| 中文描述： | 5500 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | LEAD FREE, TQFP-48 |
| 文件頁數(shù)： | 10/43頁 |
| 文件大?。?/td> | 867K |
| 代理商： | ISPPAC-CLK5510V-01TN48C |
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Lattice Semiconductor
ispClock5500 Family Data Sheet
10
Performance Characteristics – PLL
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
f
REF
Reference input frequency
range
10
—
320
MHz
t
CLOCKHI,
t
CLOCKLO
t
RINP,
t
FINP
M
DIV
N
DIV
Reference input clock HIGH and
LOW times
1.25
—
—
ns
Input rise and fall times
Measured between 20% and 80%
levels
—
—
5
ns
M-divider range
1
—
32
N-Divider range
1
—
32
f
PFD
Phase detector input frequency
range
2
10
—
320
MHz
f
VCO
V
DIV
VCO operating frequency
320
—
640
MHz
Output Divider range
Even integer values only
2
—
64
f
OUT
Output frequency range
1
Fine Skew Mode,
f
VCO
= 640MHz
Coarse Skew Mode,
f
VCO
= 640MHz
1000 cycle sample
3
10
—
320
MHz
5
—
160
MHz
t
JIT
(cc)
t
JIT
(per)
Output adjacent-cycle jitter
—
55
70
ps (p-p)
Output period jitter
Note 3
Output type LVDS, V
CCO
= 3.3V
5
Output type LVCMOS 3.3V
5
f
OUT
< 100 MHz
Inputs and Outputs con
fi
gured to
LVCMOS 3.3V standard
—
11
14
ps (RMS)
DC
ERR
Output duty cycle error (see
Table 3 for nominal values)
4
—
—
260
ps
—
—
300
ps
t
CO_BYPASS
Reference clock to output delay,
PLL bypass mode
—
5
—
ns
t
L
PLL Lock time
From Power-up event
—
150
500
μs
From Reset event
—
15
50
μs
PSR
Power supply rejection, period
jitter vs. power supply noise
f
IN
= f
OUT
= 100MHz
VCCA = VCCD = VCCO modulated
with 100kHz sinusoidal stimulus
—
0.05
—
1. In PLL Bypass mode (PLL_BYPASS = HIGH), output will support frequencies down to 0Hz (divider chain is a fully static design).
2. Dividers should be set so that they provide the phase detector with signals of 10MHz or greater for loop stability.
3. f
IN
= f
OUT
= 100 MHz, M = N = 1, V = 6, output type LVTTL, fastest slew rate, 50
output impedance.
4. Variation in duty cycle expressed in ps. To obtain duty cycle percentage error (%
ERR
) for a given output frequency (f
OUT
), %
ERR
= 100 x
f
OUT
x DC
ERR.
5. See Figures 3-5 for output loads.
ps(RMS)
mV(p-p)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK5510V-01TN48I | LED Area Light; Forward Current:300mA; Operating Temperature Range:0 C to +50 C; LED Color:Red; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA |
| ISPPAC-CLK5610V-01T100I | Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:1.6A; Supply Voltage:24VDC; Wavelength:470nm |
| ISPCLOCK5600 | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01T100C | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5620V-01T100C | LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:470nm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5510V-01TN48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5510V-01TN48I | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5510V-01TN48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5520V-01T100C | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5520V-01T100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
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