參數(shù)資料
型號(hào)： ISPPAC-CLK5510V-01T48I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： 時(shí)鐘及定時(shí)
英文描述： In-System Programmable Clock Generator with Universal Fan-Out Buffer
中文描述： 5500 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
封裝： TQFP-48
文件頁(yè)數(shù)： 28/43頁(yè)
文件大?。?/td> 867K
代理商： ISPPAC-CLK5510V-01T48I
Lattice Semiconductor
ispClock5500 Family Data Sheet
28
One can also program a user-de
fi
ned skew between two outputs using the skew control units. Because the pro-
grammable skew is derived from the VCO frequency, as described in the previous section, the absolute skew is
very accurate. The typical error for any non-zero skew setting is given by the t
SKERR
speci
fi
cation. For example, if
one is in
fi
ne skew mode with a VCO frequency of 500MHz, and selects a skew of 8TU, the realized skew will be
2ns, which will typically be accurate to within +/-30 ps. An example of error vs. skew setting can be found in the
chart ‘Typical Skew Error vs. Setting’ in the typical performance characteristics section. Note that this parameter
adds to output-to-output skew error only if the two outputs have
different
skew settings. The Bank1A and Bank3A
outputs in Figure 24 show how the various sources of skew error stack up in this case. Note that if two or more out-
puts are programmed to the same skew setting, then the contribution of the t
SKERR
skew error term does not apply.
When outputs are con
fi
gured or loaded differently, this also has an effect on skew matching. If an output is set to
support a different logic type, this can be accounted for by using the t
IOO
output adders speci
fi
ed in the Table
‘Switching Characteristics’. That table speci
fi
es the additional skew added to an output using LVPECL as a base-
line. For instance, if one output is speci
fi
ed as LVTTL (t
IOO
= 0.1ns), and another output is speci
fi
ed as LVPECL
(t
IOO
= 0ns), then one could expect 0.1ns of additional skew between the two outputs. This timing relationship is
shown in Figure 25a.
Figure 25. Output Timing Adders for Logic Type (a) and Output Slew Rate (b)
Similarly, when one changes the slew rate of an output, the output slew rate adders (t
IOS
) can be used to predict
the resulting skew. In this case, the fastest slew setting (1) is used as the baseline against which other slews are
measured. For example, in the case of outputs con
fi
gured to the same logic type (e.g. LVCMOS 1.8V), if one output
is set to the fastest slew rate (1, t
IOS
= 0ps), and another set to slew rate 3 (t
IOS
= 660ps), then one could expect
660ps of skew between the two outputs, as shown in Figure 25b.
Other Features
Pro
fi
le Select
The ispClock5500 stores all internal con
fi
guration data in on-board E
2
CMOS memory. Up to four independent con-
fi
guration pro
fi
les may be stored in each device. The choice of which con
fi
guration pro
fi
le is to be active is speci
fi
ed
thought the pro
fi
le select inputs PS0 and PS1, as shown in Table 7.
Table 7. Profile Select Function
Each pro
fi
le controls the following internal con
fi
guration items:
M divider setting
N divider setting
V divider settings
PS1
PS0
Active Pro
fi
le
0
0
Pro
fi
le 0
0
1
Pro
fi
le 1
1
0
Pro
fi
le 2
1
1
Pro
fi
le 3
LVPECL Output
(T
IOS
= 0)
LVTTL Output
(T
IOS
= 0.1ns)
0.1ns
(a)
LVCMOS Output
(Slew rate=1)
LVCMOS Output
(Slew rate=3)
660ps
(b)
相關(guān)PDF資料
PDF描述
ISPPAC-CLK5520V-01T100C LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:470nm
ISPPAC-CLK5520V-01T100I Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:800mA; Supply Voltage:24VDC; Wavelength:470nm
ISPPAC-CLK5520V-01TN100I LED Area Light; LED Color:Infrared; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:150mA; Supply Voltage:24VDC; Wavelength:940nm
ISPPAC-CLK5510V-01TN48C Backlight LED; Color:Infrared; Digit/Alpha Height:85mm; Forward Current:500mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:85x220mm; Peak Reflow Compatible (260 C):No
ISPPAC-CLK5510V-01TN48I LED Area Light; Forward Current:300mA; Operating Temperature Range:0 C to +50 C; LED Color:Red; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPACCLK5510V-01T48I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPACCLK5510V-01TN100C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPACCLK5510V-01TN100I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5510V-01TN48C 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPACCLK5510V-01TN48C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
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