- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384544 > ISPPAC-CLK5510V-01T48I (LATTICE SEMICONDUCTOR CORP) In-System Programmable Clock Generator with Universal Fan-Out Buffer PDF資料下載
參數(shù)資料
| 型號： | ISPPAC-CLK5510V-01T48I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| 中文描述： | 5500 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數(shù)： | 25/43頁 |
| 文件大?。?/td> | 867K |
| 代理商： | ISPPAC-CLK5510V-01T48I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁
Lattice Semiconductor
ispClock5500 Family Data Sheet
25
Figure 22b shows another derating curve, derived under the assumption that the output frequency is 100MHz. For
many applications, 100MHz outputs will be a more realistic scenario. Comparing the maximum temperature limits
of Figure 22b with Figure 22a, one can see that signi
fi
cantly higher operating temperatures are possible in LVC-
MOS 3.3V output mode with more outputs at 100MHz than at 320MHz.
The examples above described examples using LVCMOS 3.3V logic, which represents the maximum power dissi-
pation case at higher frequencies. For optimal operation at very high frequencies (> 150 MHz) LVDS will often be
the best choice from a signal integrity standpoint. For LVDS-con
fi
gured outputs, the maximum ICCO current con-
sumption per bank is low enough that both the ispClock5510 and ispClock5520 can operate all outputs at maxi-
mum frequency over their complete rated temperature range, as shown in Figure 22c.
Note that because of variations in circuit board mounting, construction, and layout, as well as convective and forced
air
fl
ow present in a given design, actual die operating temperature is subject to considerable variation from that
which may be theoretically predicted from package characteristics and device power dissipation.
Output Enable Controls
The ispClock5500 family provides the user with several options for enabling and disabling output pins, as well as
suspending the output clock. In addition to providing the user with the ability to reduce the device’s power con-
sumption by turning off unused drivers, these features can also be used for functional testing purposes. The follow-
ing inputs pins are used for output enable functions:
GOE – global output enable
OEX, OEY – secondary output enable controls
SGATE
– synchronous output control
Additionally, internal E
2
CMOS con
fi
guration bits are provided for the purpose of modifying the effects of these
external control pins.
When GOE is HIGH, all output drivers are forced into a high-Z state, regardless of any internal con
fi
guration. When
GOE is LOW, the output drivers may also be enabled or disabled on an individual basis, and optionally controlled
by the OEX and OEY pins. Internal E
2
CMOS con
fi
guration is used to establish whether the output driver is always
enabled (when GOE pin is LOW), never enabled (permanently off), or selectively enabled by the state of either
OEX or OEY. Bringing GOE high will also disable the internal feedback driver and will result in a loss of lock.
Synchronous output gating is provided by ispClock5500 devices through the use of the
SGATE
pin. The
SGATE
pin
does not disable the output driver, but merely forces the output to either a high or low state, depending on the out-
put driver’s polarity setting. If the output driver polarity is true, the output will be forced LOW when
SGATE
is
brought LOW, while if it is inverted, the output will be forced HIGH. A primary feature of the
SGATE
function is that
the clock output is enabled and disabled synchronous to the selected internal clock source. This prevents the gen-
eration of partial, ‘runt’, output clock pulses, which would otherwise occur with simple combinatorial gating
schemes. The
SGATE
is available to all clock outputs and is selectable on a pin-by-pin basis.
Table 5 shows the behavior of the outputs for various combinations of the output enables,
SGATE
input, and
E
2
CMOS con
fi
guration.
Table 5. Clock Output Enable Functions
GOE
OEX
OEY
E
2
Con
fi
guration
Output
X
X
X
Always OFF
High-Z
0
X
X
Always ON
Clock Out
0
0
X
Enable on OEX
Clock Out
0
1
X
Enable on OEX
High-Z
0
X
0
Enable on OEY
Clock Out
0
X
1
Enable on OEY
High-Z
1
X
X
n/a
High-Z
相關PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK5520V-01T100C | LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:470nm |
| ISPPAC-CLK5520V-01T100I | Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:800mA; Supply Voltage:24VDC; Wavelength:470nm |
| ISPPAC-CLK5520V-01TN100I | LED Area Light; LED Color:Infrared; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:150mA; Supply Voltage:24VDC; Wavelength:940nm |
| ISPPAC-CLK5510V-01TN48C | Backlight LED; Color:Infrared; Digit/Alpha Height:85mm; Forward Current:500mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:85x220mm; Peak Reflow Compatible (260 C):No |
| ISPPAC-CLK5510V-01TN48I | LED Area Light; Forward Current:300mA; Operating Temperature Range:0 C to +50 C; LED Color:Red; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5510V-01T48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPACCLK5510V-01TN100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPACCLK5510V-01TN100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5510V-01TN48C | 功能描述:時鐘驅動器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5510V-01TN48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
發(fā)布緊急采購，3分鐘左右您將得到回復。