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參數(shù)資料
| 型號： | ISPPAC-CLK5510V-01T48C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| 中文描述： | 5500 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數(shù)： | 2/43頁 |
| 文件大?。?/td> | 867K |
| 代理商： | ISPPAC-CLK5510V-01T48C |
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Lattice Semiconductor
ispClock5500 Family Data Sheet
2
General Description and Overview
The ispClock5510 and ispClock5520 are in-system-programmable high-fanout PLL-based clock drivers designed
for use in high performance communications and computing applications. The ispClock5510 provides up to 10 sin-
gle-ended or
fi
ve differential clock outputs, while the ispClock5520 provides up to 20 single-ended or 10 differential
clock outputs. Each pair of outputs may be independently con
fi
gured to support separate I/O standards (LVDS,
LVPECL, LVTTL, LVCMOS, SSTL, HSTL) and output frequency. In addition, each output provides independent pro-
grammable control of termination, slew-rate, and timing skew. All con
fi
guration information is stored on-chip in non-
volatile E
CMOS memory.
2
The ispClock5500’s PLL and divider systems supports the synthesis of clock frequencies differing from that of the
reference input through the provision of programmable input and feedback dividers. A set of
fi
ve post-PLL V-divid-
ers provides additional
fl
exibility by supporting the generation of
fi
ve separate output frequencies. Loop feedback
may be taken from the output of any of the
fi
ve V-dividers.
The core functions of all members of the ispClock5500 family are identical, the differences between devices being
restricted to the number of inputs and outputs, as shown in the following table.
Table 1. ispClock5500 Family Members
Figure 1. ispClock5510 Functional Block Diagram
Device
Ref. Input Pairs
Clock Outputs
ispClock5510
1
10
ispClock5520
2
20
VCO
LOOP
FILTER
PHASE
DETECT
LOCK
DETECT
M
N
INPUT
DIVIDER
FEEDBACK
SKEW ADJUST
1
0
FEEDBACK
DIVIDER
GOE
OEX
LOCK
PLL_BYPASS
JTAG INTERFACE
OEY
TDI
TMS
TCK
TDO
SGATE
SKEW
CONTROL
OUTPUT
DRIVERS
BANK_3A
BANK_3B
BANK_4A
BANK_4B
OUTPUT
DIVIDERS
OUTPUT ROUTING
MATRIX
RESET
V1
V0
V3
V4
BANK_0A
BANK_0B
BANK_1A
BANK_1B
BANK_2A
BANK_2B
PS0
PS1
Profile Select
Control
0
1
2
3
OUTPUT ENABLE CONTROLS
(1-32)
(1-32)
(2-64)
(2-64)
(2-64)
(2-64)
(2-64)
REFA+
REFA-
REFVTT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK5510V-01T48I | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5520V-01T100C | LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:470nm |
| ISPPAC-CLK5520V-01T100I | Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:800mA; Supply Voltage:24VDC; Wavelength:470nm |
| ISPPAC-CLK5520V-01TN100I | LED Area Light; LED Color:Infrared; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:150mA; Supply Voltage:24VDC; Wavelength:940nm |
| ISPPAC-CLK5510V-01TN48C | Backlight LED; Color:Infrared; Digit/Alpha Height:85mm; Forward Current:500mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:85x220mm; Peak Reflow Compatible (260 C):No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5510V-01T48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5510V-01T48I | 功能描述:時鐘驅(qū)動器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5510V-01T48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPACCLK5510V-01TN100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPACCLK5510V-01TN100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
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