參數(shù)資料
型號(hào)： ISPPAC-CLK5510V-01T48C
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： 時(shí)鐘及定時(shí)
英文描述： In-System Programmable Clock Generator with Universal Fan-Out Buffer
中文描述： 5500 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
封裝： TQFP-48
文件頁(yè)數(shù)： 17/43頁(yè)
文件大小： 867K
代理商： ISPPAC-CLK5510V-01T48C
Lattice Semiconductor
ispClock5500 Family Data Sheet
17
Table 3. Nominal Output Duty Cycle vs. V Divider Setting
PLL_BYPASS Mode
The PLL_BYPASS mode is provided so that input reference signals can be coupled through to the outputs without
using the PLL functions. When PLL_BYPASS mode is enabled (PLL_BYPASS=HIGH), the output of the M divider
is routed directly to the inputs of the V dividers. In PLL_BYPASS mode, the nominal values of the V dividers are
halved, so that they provide division ratios ranging from 1 to 32. The divide-by-1 setting, however, is invalid and will
produce unde
fi
ned results. The output frequency for a given V divider (f
k
) will be determined by
(2)
Please note that PLL_BYPASS mode is provided primarily for testing purposes. When PLL_BYPASS mode is
enabled, features such as lock detect and skew generation are unavailable.
Reference Inputs
The ispClock5500 provides sets of con
fi
gurable, internally-terminated inputs for clock reference signals. In normal
operation, the clock reference input (REFA) is connected to the system clock from which the output signals are to
be derived.
The ispClock5510 provides one input signal pair for reference input, while the ispClock5520 provides two input
pairs for reference signals. To select between reference inputs, the ispClock5520 provides a CMOS-compatible dig-
ital input called REFSEL. Table 4 shows the behavior of this control input:
Table 4. REFSEL Operation for ispClock5520
Clock reference inputs may be con
fi
gured to interface to signals from the following logic families with little or no
external support circuitry:
LVTTL (3.3V)
LVCMOS (1.8V, 2.5V, 3.3V)
SSTL2
SSTL3
HSTL
LVDS
LVPECL (differential, 3.3V)
Each input also features internal programmable termination resistors, as shown in Figure 12.
V
DC%
V
DC%
V
DC%
V
DC%
2
50
18
44
34
47
50
48
4
50
20
50
36
50
52
50
6
67
22
45
38
47
54
48
8
50
24
50
40
50
56
50
10
40
26
46
42
48
58
48
12
50
28
50
44
50
60
50
14
43
30
47
46
48
62
48
16
50
32
50
48
50
64
50
REFSEL
Selected Input Pair
0
REFA+/-
1
REFB+/-
=
f
k
f
ref
M x V
k
相關(guān)PDF資料
PDF描述
ISPPAC-CLK5510V-01T48I In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5520V-01T100C LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:470nm
ISPPAC-CLK5520V-01T100I Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:800mA; Supply Voltage:24VDC; Wavelength:470nm
ISPPAC-CLK5520V-01TN100I LED Area Light; LED Color:Infrared; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:150mA; Supply Voltage:24VDC; Wavelength:940nm
ISPPAC-CLK5510V-01TN48C Backlight LED; Color:Infrared; Digit/Alpha Height:85mm; Forward Current:500mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:85x220mm; Peak Reflow Compatible (260 C):No
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPACCLK5510V-01T48C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5510V-01T48I 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPACCLK5510V-01T48I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPACCLK5510V-01TN100C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPACCLK5510V-01TN100I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
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