參數(shù)資料
型號(hào)： ISPLSI8840-60LB432
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： In-System Programmable SuperBIG⑩ High Density PLD
中文描述： EE PLD, 24 ns, PBGA432
封裝： BGA-432
文件頁(yè)數(shù)： 8/23頁(yè)
文件大?。?/td> 304K
代理商： ISPLSI8840-60LB432
Specifications
ispLSI 8840
8
Output Control Organization
In addition to the data input and output to the I/O cells,
each I/O cell can have up to six different I/O cell control
signals. In addition to the internal OE control, the five
control signals for each I/O cell consist of pin OE control,
clock enable, clock input, asynchronous preset and asyn-
chronous reset. All of the I/O control signals can be driven
either from the dedicated external input pins or from the
internal control bus.
The output enable of each I/O cell can be driven by 21
different sources
–
16 from the output control bus, four
from the Global OE pins and one from the Test OE pin.
Figure 5. Output Control Bus and Quadrant Organization
Quadrant 0, 16-Bit Wide Output Control Bus
(I/O B0-B6 <0-11>, QIOCLK0)
Quadrant 2, 16-Bit Wide Output Control Bus
(I/O B0-B6 <12-23>, QIOCLK2)
Q
(
Q
(
GLB
Generated
Output
Control
(see Figure 2)
From PT81
OE Bus.eps
The Global OE signals and Test OE signal are driven
from the dedicated external control input pins.
The 16-bit wide output control buses are organized in four
different quadrants as shown in Figure 5. Since each
GLB is capable of generating the output control signals,
each of the output control bus signals can be driven from
a unique GLB. The 42 GLBs can generate a total of 42
unique I/O control signals. Referring to Figure 2, the GLB
generates its output control signal from control product
term (PT81).
Figure 5 also illustrates how the quadrant clocks are
routed to the appropriate quadrant I/O cells.
相關(guān)PDF資料
PDF描述
ISPLSI8840-90LB432 In-System Programmable SuperBIG⑩ High Density PLD
ISPMACH4ACPLDFAMILY High Performance E 2 CMOS In-System Programmable Logic
ISPPAC-CLK5520V-01TN100C Linear Array Light; LED Color:Green; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:1.6A; Supply Voltage:24VDC; Wavelength:530nm
ISPPAC-CLK55xx In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5510V In-System Programmable Clock Generator with Universal Fan-Out Buffer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPLSI8840-90LB432 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 5000MV HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ISPLSI-8840V-125LB272 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述:
ispLSI8840V-125LB272 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 5000MV RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ISPLSI8840V-125LB492 制造商:Rochester Electronics LLC 功能描述:- Bulk
ISPLSI-8840V-60LB272 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*