參數(shù)資料
型號(hào)： ISPLSI81080V-125LB492
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： 3.3V In-System Programmable SuperBIG⑩ High Density PLD
中文描述： EE PLD, 14.5 ns, PBGA492
封裝： BGA-492
文件頁數(shù)： 15/26頁
文件大小： 333K
代理商： ISPLSI81080V-125LB492
Specifications
ispLSI 81080V
15
Internal Timing Parameters
Over Recommended Operating Conditions
I/O Cell Delay
t
idcom
t
idreg
t
obp
t
ibp
t
iolat
t
ioco
t
iosu
t
ioh
t
iorst
t
iosuce
t
iohce
t
odreg
t
odcom
t
odz
t
slf
t
sls
GLB / Macrocell Delay
t
andhs
39 AND Array, High Speed Mode
t
andlp
40 AND Array, Low Power Mode
t
1pt
41 Single Product Term Bypass
t
4ptcom 42 Four Product Term Bypass, Combinatorial Macrocell
t
4ptreg
43 Four Product Term Bypass, Registered Macrocell
t
ptsa
44 Product Term Sharing Array
t
mbp
45 Macrocell Register/Latch Bypass
t
mlat
46 Macrocell Latch, Transparent Mode
t
mco
47 Macrocell Register/Latch, Clk/Gate to Output
t
msu
48 Macrocell Register/Latch, Setup Time
t
mh
49 Macrocell Register/Latch, Hold Time
t
mrst
50 Macrocell Register/Latch, Reset or Set Time
t
msuce
51 Macrocell Register/Latch, Setup Time for Clk Enable
t
mhce
52 Macrocell Register/Latch, Hold Time for Clk Enable
t
floc
54 Local Feedback to AND Array
t
pck
55 Single Product Term, Clk
t
pcken
56 Single Product Term, Clk Enable
t
sck
57 Shared Product Term, Clk
t
scken
58 Shared Product Term, Clk Enable
t
prst
59 Single Product Term, Reset or Set Delay
t
rdir
60 Macrocell Register, Direct Input from GRP
23 Input Pad and Input Buffer, Combinatorial Input
24 Input Pad and Input Buffer, Registered Input
25 Output Register/Latch Bypass to Output Buffer
26 Input Register/Latch Bypass to BFM Routing or GRP
27 I/O Cell Latch, Transparent Mode
28 I/O Cell Register/Latch, Clk/Gate to Output
29 I/O Cell Register/Latch, Setup Time
30 I/O Cell Register/Latch, Hold Time
31 I/O Cell Register/Latch, Reset or Set Time
32 I/O Cell Register/Latch, Setup Time for Clk Enable
33 I/O cell Register/Latch, Hold Time for Clk Enable
34 I/O Cell Output Buffer Delay, Registered Output
35 I/O Cell Output Buffer Delay, Combinatorial Output
36 Output Driver Disable Time
37 Slew Rate Adder, Fast Slew Rate
38 Slew Rate Adder, Slow Slew Rate
–
–
–
–
–
–
0.3
6.4
0.0
0.4
2.0
0.5
–
–
1.5
–
–
1.6
1.6
1.4
0.0
6.2
–
–
–
–
–
–
0.4
7.6
0.0
0.5
2.4
1.2
–
–
1.7
–
–
1.9
1.9
1.7
0.0
7.3
–
–
–
–
–
–
0.6
11.2
0.0
0.8
3.6
1.6
–
–
2.5
–
–
2.9
2.9
2.6
0.0
10.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.5
2.5
–
0.9
4.6
–
–
–
–
–
2.4
3.2
–
1.0
4.6
–
–
–
–
–
3.9
4.7
–
1.2
6.9
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2.6
6.5
1.9
0.5
1.4
2.4
0.0
4.6
0.2
–
–
1.4
–
–
0.1
1.3
1.7
1.9
1.9
1.5
7.2
–
–
–
–
–
–
–
–
–
2.9
7.7
2.2
0.6
1.7
2.7
0.0
5.5
0.8
–
–
1.5
–
–
0.1
1.6
2.0
2.3
2.3
1.7
8.4
–
–
–
–
–
–
–
–
–
4.2
11.5
3.4
0.9
2.2
4.1
0.0
8.2
0.9
–
–
1.6
–
–
0.6
2.5
3.1
3.5
3.5
2.6
12.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.7
1.0
–
1.0
2.3
–
1.3
–
1.7
1.7
–
–
4.5
1.2
–
1.3
2.6
–
1.6
–
2.0
2.0
–
–
6.9
1.1
–
1.7
3.9
–
2.5
–
3.1
3.1
–
–
-125
-90
-60
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
PARA-
METER #
2
DESCRIPTION
相關(guān)PDF資料
PDF描述
ISPLSI81080V-90LB492 3.3V In-System Programmable SuperBIG⑩ High Density PLD
ISPLSI8600V-125LB272 3.3V In-System Programmable SuperBIG⑩ High Density PLD
ISPLSI8600V-125LB492 3.3V In-System Programmable SuperBIG⑩ High Density PLD
ISPLSI8600V-60LB272 3.3V In-System Programmable SuperBIG⑩ High Density PLD
ISPLSI8600V-60LB492 3.3V In-System Programmable SuperBIG⑩ High Density PLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPLSI81080V-60LB272 制造商:Rochester Electronics LLC 功能描述:- Bulk
ISPLSI81080V-60LB272I 制造商:Rochester Electronics LLC 功能描述:- Bulk
ISPLSI81080V-60LB492 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Lattice Semiconductor Corporation 功能描述:
ISPLSI81080V-90LB272 制造商:Rochester Electronics LLC 功能描述:- Bulk
ISPLSI81080V-90LB492 制造商:Rochester Electronics LLC 功能描述:- Bulk
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