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參數(shù)資料
| 型號(hào)： | ISPLSI2128V-80LT176 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | 3.3V High Density Programmable Logic |
| 中文描述： | EE PLD, 15 ns, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 151K |
| 代理商： | ISPLSI2128V-80LT176 |
Specifications
ispLSI 2128V
5
USEispLS 2128VEFORNEWDESGNS
External Timing Parameters
Over Recommended Operating Conditions
t
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
UNITS
-80
MIN.
–
80.0
TEST
COND.
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030/2128V
1
4
3
1
tsu2 + tco1
( )
-60
MIN.
–
61.7
MAX.
15.0
MAX.
20.0
DESCRIPTION
#
2
PARAMETER
A
A
3
Data Propagation Delay
Clock Frequency with Internal Feedback
ns
MHz
–
–
–
–
–
A
–
4
5
6
7
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
–
–
–
–
–
–
MHz
MHz
ns
ns
ns
–
–
0.0
–
–
–
–
A
–
B
C
B
C
9
GLB Reg. Setup Time before Clock
GLB Reg. Clock to Output Delay
GLB Reg. Hold Time after Clock
Ext. Reset Pin to Output Delay
Ext. Reset Pulse Duration
Input to Output Enable
Input to Output Disable
Global OE Output Enable
Global OE Output Disable
9.0
–
0.0
–
7.0
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
13
14
15
16
17
–
–
–
–
–
–
–
–
–
–
18
19
External Synchronous Clock Pulse Duration, High
External Synchronous Clock Pulse Duration, Low
5.0
5.0
–
–
–
–
ns
ns
64.5
100
7.0
6.5
–
–
7.5
–
14.0
–
15.0
15.0
10.0
10.0
51.3
71.4
9.0
0.0
11.0
0.0
8.0
7.0
7.0
8.5
9.5
16.0
18.0
18.0
12.0
12.0
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| ISPLSI2128V-60LJ84 | 3.3V High Density Programmable Logic |
| ISPLSI2128V-60LJ84I | 3.3V High Density Programmable Logic |
| ISPLSI2128V-60LT100 | 3.3V High Density Programmable Logic |
| ISPLSI2128V-80LT176I | 3.3V High Density Programmable Logic |
| ISPLSI2128V | 3.3V High Density Programmable Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI2128V-80LT176I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
| ISPLSI2128VE | 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPLSI2128VE_04 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V In-System Programmable SuperFAST⑩ High Density PLD |
| ISPLSI2128VE100LB100 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V In-System Programmable SuperFAST⑩ High Density PLD |
| ISPLSI2128VE-100LB100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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