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參數(shù)資料
| 型號(hào)： | ISPLSI2128V-80LT176 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | 3.3V High Density Programmable Logic |
| 中文描述： | EE PLD, 15 ns, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 151K |
| 代理商： | ISPLSI2128V-80LT176 |
Specifications
ispLSI 2128V
2
USEispLS 2128VEFORNEWDESGNS
minimize timing skew.
Functional Block Diagram
Figure 1. ispLSI 2128V Functional Block Diagram (128-I/O and 64-I/O Versions)
The 128-I/O 2128V contains 128 I/O cells, while the 64-
I/O version contains 64 I/O cells. Each I/O cell is directly
connected to an I/O pin and can be individually pro-
grammed to be a combinatorial input, output or
bi-directional I/O pin with 3-state control. The signal
levels are TTL compatible voltages and the output drivers
can source 4mA or sink 8mA. Each output can be
programmed independently for fast or slow output slew
rate to minimize overall output switching noise. Device
pins can be safely driven to 5V signal levels to support
mixed-voltage systems.
Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and
two or one ORPs are connected together to make a
Megablock (see Figure 1). The outputs of the eight GLBs
are connected to a set of 32 or 16 universal I/O cells by
the two or one ORPs. Each ispLSI 2128V device contains
four Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
Clocks in the ispLSI 2128V device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2128V are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. When this fuse is erased (JEDEC “1”),
the output is configured as a totem-pole output. When
this fuse is programmed (JEDEC “0”), the output is
configured as an open-drain. The default configuration
when the device is in bulk erased state is totem-pole
configuration. The open-drain/totem-pole option is se-
lectable through the ispDesignEXPERT software tools.
Global
Routing
Pool
(GRP)
0139B/2128V
Megablock
RESET
Input Bus
D3
D2
D1
D0
D7
D6
D5
D4
Output Routing Pool (ORP)
Output Routing Pool (ORP)
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I
I
I
I
I
I
I
C7
C6
C5
C4
C3
C2
C1
C0
I
IN 5
IN 4
I/O 91
I/O 90
I/O 89
I/O 88
I/O 87
I/O 86
I/O 85
I/O 84
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 95
I/O 94
I/O 93
I/O 92
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
C
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Y
Y
Y
T
T
B4
B5
B6
B7
B0
B1
B2
B3
A0
A1
A2
A3
A4
A5
A6
A7
ispEN
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 0
I/O 1
I/O 2
I/O 3
GOE 1
C
C
I
TDI/IN 0
TMS/IN 1
I
Generic Logic
Blocks (GLBs)
Global
Routing
Pool
(GRP)
0139B/2128V.64IO
Megablock
RESET
Input Bus
D3
D2
D1
D0
D7
D6
D5
D4
Output Routing Pool (ORP)
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I
I
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I
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C7
C6
C5
C4
C3
C2
C1
C0
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IN 5*
IN 4*
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
I/O 47
I/O 46
I/O 45
I/O 44
Output Routing Pool (ORP)
Input Bus
C
Y
Y
Y
T
T
B4
B5
B6
B7
B0
B1
B2
B3
A0
A1
A2
A3
A4
A5
A6
A7
ispEN
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
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I
I
I
I
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I
I
I
I/O 0
I/O 1
I/O 2
I/O 3
GOE 1
C
C
I
TDI/IN 0
TMS/IN 1
*Not available on 84-PLCC Device
I
Generic Logic
Blocks (GLBs)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPLSI2128V-60LJ84 | 3.3V High Density Programmable Logic |
| ISPLSI2128V-60LJ84I | 3.3V High Density Programmable Logic |
| ISPLSI2128V-60LT100 | 3.3V High Density Programmable Logic |
| ISPLSI2128V-80LT176I | 3.3V High Density Programmable Logic |
| ISPLSI2128V | 3.3V High Density Programmable Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI2128V-80LT176I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
| ISPLSI2128VE | 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPLSI2128VE_04 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V In-System Programmable SuperFAST⑩ High Density PLD |
| ISPLSI2128VE100LB100 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V In-System Programmable SuperFAST⑩ High Density PLD |
| ISPLSI2128VE-100LB100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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