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參數(shù)資料
| 型號： | ISPLSI2032-110LT48I |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable High Density PLD |
| 中文描述： | 在系統(tǒng)可編程高密度可編程邏輯器件 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 153K |
| 代理商： | ISPLSI2032-110LT48I |
Specifications
ispLSI 2032/A
2
(Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the ORP. Each ispLSI
2032 and 2032A device contains one Megablock.
Functional Block Diagram
Figure 1. ispLSI 2032/A Functional Block Diagram
Global Routing Pool
(GRP)
A0
A1
A3
I
O
A7
A6
A5
A4
I
O
A2
C
C
C
GOE 0
Notes:
*Y1 and RESET are multiplexed on the same pin
I/O 0
I/O 1
I/O 2
I/O 3
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16
SDI/IN 0
SDO/IN 1
I/O 4
I/O 5
Y0
*Y1/
RESET
SCLK/Y2
ispEN
MODE
0139B(1)isp/2000
The devices also have 32 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2032 and 2032A devices are se-
lected using the dedicated clock pins. Three dedicated
clock pins (Y0, Y1, Y2) or an asynchronous clock can be
selected on a GLB basis. The asynchronous or Product
Term clock can be generated in any GLB for its own clock.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPLSI2032-135LJ | In-System Programmable High Density PLD |
| ISPLSI2032-135LJI | In-System Programmable High Density PLD |
| ISPLSI2032-135LT44 | In-System Programmable High Density PLD |
| ISPLSI2032-135LT44I | In-System Programmable High Density PLD |
| ISPLSI2032-135LT48 | In-System Programmable High Density PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI2032-135LJ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ISPLSI2032-135LJI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ISPLSI2032-135LT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| ISPLSI-2032-135LT44 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
| ispLSI2032-135LT44 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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