參數(shù)資料
型號(hào)： ISPLSI2032-110LT48I
廠商： Lattice Semiconductor Corporation
英文描述： In-System Programmable High Density PLD
中文描述： 在系統(tǒng)可編程高密度可編程邏輯器件
文件頁(yè)數(shù)： 11/15頁(yè)
文件大?。?/td> 153K
代理商： ISPLSI2032-110LT48I
Specifications
ispLSI 2032/A
11
Pin Description
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
Input/Output Pins — These are the general purpose
NAME
44-PIN PLCC
PIN NUMBERS
DESCRIPTION
15,
25,
29,
37,
41,
3,
7,
16,
26,
30,
38,
42,
4,
8,
17,
27,
31,
39,
43,
5,
9,
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
18,
22,
28,
32,
40,
44,
6,
10
Global Output Enable input pin.
2
GOE 0
1,
23
GND
V
CC
No Connect.
12, 34
17, 39
6,
28
18, 42
6,
30
VCC
NC
1
12, 24, 36, 48
Ground (GND)
Input — This pin performs two functions. When
ispEN
is logic low, it functions as an input pin to load
programming data into the device. SDI/IN0 also is used
as one of the two control pins for the isp state machine.
When
ispEN
is high, it functions as a dedicated input
pin.
Dedicated Clock input. This clock input is connected to
one of the clock inputs of all the GLBs on the device.
This pin performs two functions:
- Dedicated clock input. This clock input is brought
into the Clock Distribution Network, and can optionally
be routed to any GLB and/or I/O cell on the device.
- Active Low (0) Reset pin which resets all of the GLB
and I/O registers in the device.
Input — Dedicated in-system programming enable
input pin. This pin is brought low to enable the
programming mode. The MODE, SDI, SDO and SCLK
controls become active.
RESET
/Y1
Y0
SDI/IN 0
2
ispEN
MODE
Input — When in ISP Mode, controls operation of ISP
state machine.
Output/Input — This pin performs two functions. When
ispEN
is logic low, it functions as an output pin to read
serial shift register data. When
ispEN
is high, it
functions as a dedicated input pin.
SDO/IN 1
2
Input — This pin performs two functions. When
ispEN
is logic low, it functions as a clock pin for the
Serial Shift Register. When
ispEN
is high, it
functions as a dedicated clock input. This clock input
is brought into the Clock Distribution Network and
can be routed to any GLB and/or I/O cell on the
device.
SCLK/Y2
2
35
11
14
13
36
24
33
44-PIN TQFP
PIN NUMBERS
48-PIN TQFP
PIN NUMBERS
9,
13,
19,
23,
31
35,
41,
1,
40
10,
14,
20,
24,
32,
36,
42,
2,
11,
15,
21,
25,
33,
37,
43,
3,
12,
16,
22,
26,
34,
38,
44,
4
5
29
7
8
30
18
27
9,
14,
20,
25,
33,
38,
44,
1,
43
10,
15,
21,
26,
34,
39,
45,
2,
11,
16,
22,
27,
35,
40,
46,
3,
13,
17,
23,
28,
37,
41,
47,
4
5
31
7
8
32
19
29
相關(guān)PDF資料
PDF描述
ISPLSI2032-135LJ In-System Programmable High Density PLD
ISPLSI2032-135LJI In-System Programmable High Density PLD
ISPLSI2032-135LT44 In-System Programmable High Density PLD
ISPLSI2032-135LT44I In-System Programmable High Density PLD
ISPLSI2032-135LT48 In-System Programmable High Density PLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPLSI2032-135LJ 制造商:Rochester Electronics LLC 功能描述:- Bulk
ISPLSI2032-135LJI 制造商:Rochester Electronics LLC 功能描述:- Bulk
ISPLSI2032-135LT 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Electrically-Erasable Complex PLD
ISPLSI-2032-135LT44 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述:
ispLSI2032-135LT44 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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