參數(shù)資料
型號: ISPLSI1048EA-170LQ128
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: In-System Programmable High Density PLD
中文描述: EE PLD, 7 ns, PQFP128
封裝: PLASTIC, QFP-128
文件頁數(shù): 6/14頁
文件大?。?/td> 182K
代理商: ISPLSI1048EA-170LQ128
Specifications
ispLSI 1048EA
6
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
t
pd2
f
max (Int.)
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
UNITS
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model
in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030A/1048EA
v.2.0
1
4
3
1
( )
DESCRIPTION
#
2
PARAMETER
A
A
A
1
2
3
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback
ns
ns
MHz
4
5
6
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
GLB Reg. Setup Time before Clock,4 PT Bypass
MHz
MHz
ns
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
ns
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
ns
A
B
C
B
C
9
GLB Reg. Setup Time before Clock
GLB Reg. Clock to Output Delay
GLB Reg. Hold Time after Clock
Ext. Reset Pin to Output Delay
Ext. Reset Pulse Duration
Input to Output Enable
Input to Output Disable
Global OE Output Enable
Global OE Output Disable
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
13
14
15
16
17
t
wh
t
wl
t
su3
t
h3
18
19
External Synchronous Clock Pulse Duration, High
External Synchronous Clock Pulse Duration, Low
ns
ns
20
I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3)
ns
21
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
ns
( )
1
-125
MIN. MAX.
125
7.5
10.0
0.0
5.5
0.0
5.0
3.0
3.0
3.0
0.0
100
167
4.5
4.5
5.5
10.0
12.0
12.0
7.0
7.0
-170
MIN. MAX.
170
5.0
7.0
0.0
4.5
0.0
4.0
2.25
2.25
3.0
0.0
125
222
3.5
3.5
4.5
7.0
9.0
9.0
6.5
6.5
-100
MIN. MAX.
100
10.0
12.5
7.0
0.0
6.5
4.0
4.0
77
125
6.0
0.0
7.0
3.5
0.0
6.0
13.5
15.0
15.0
9.0
9.0
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