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參數(shù)資料
| 型號(hào)： | ISPLSI1048EA-170LQ128 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | In-System Programmable High Density PLD |
| 中文描述： | EE PLD, 7 ns, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 182K |
| 代理商： | ISPLSI1048EA-170LQ128 |
Specifications
ispLSI 1048EA
10
0127/1048EA
Icc can be estimated for the ispLSI 1048EA using the following equation:
Icc = 20mA + (# of PTs * .45) + (# of nets * Max Freq * .0087)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The Icc estimate is based on typical conditions (Vcc = 5.0V, room temperature) and an assumption of four GLB
loads on average exists. These values are for estimates only. Since the value of Icc is sensitive to operating
conditions and the program in the device, the actual Icc should be verified.
f
max (MHz)
Notes: Configuration of twelve 16-bit counters, Typical current at 5V, 25
C
400
300
200
100
0
25
50
75
100
125
150
175
I
C
ispLSI 1048EA
500
Power Consumption
Power consumption in the ispLSI 1048EA device de-
pends on two primary factors: the speed at which the
device is operating and the number of Product Terms
used. Figure 4 shows the relationship between power
and operating speed.
Figure 4. Typical Device Power Consumption vs fmax
Package Thermal Characteristics
For the ispLSI 1048EA-170, it is strongly recommended
that the actual Icc be verified to ensure that the maximum
junction temperature (T
J
) with power supplied is not
exceeded. Depending on the specific logic design and
clock speed, airflow may be required to satisfy the maxi-
mum allowable junction temperature (T
J
) specification.
Please refer to the Thermal Management section of the
Lattice Semiconductor Data Book or CD-ROM for addi-
tional information on calculating T
J
.
Maximum GRP Delay vs. GLB Loads
GLB Load
3
1
8
16
32
48
G 4
5
4
2
GRP/GLB/1048EA
1
ispLSI 1048EA-170
ispLSI 1048EA-125
ispLSI 1048EA-100
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPLSI1048EA-100LQ128 | In-System Programmable High Density PLD |
| ISPLSI1048EA-100LT128 | In-System Programmable High Density PLD |
| ISPLSI1048EA-125LT128 | In-System Programmable High Density PLD |
| ISPLSI1048EA-170LT128 | In-System Programmable High Density PLD |
| ISPLSI2032-150LJ | In-System Programmable High Density PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI1048EA-170LT128 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2030A-110LJ44 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| ISPLSI2030A-110LT44 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| ISPLSI2030A-110LT48 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| ISPLSI2030A-135LJ44 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
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