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參數(shù)資料
| 型號(hào)： | ISPLSI1032E-80LT |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High-Density Programmable Logic |
| 中文描述： | 高密度可編程邏輯 |
| 文件頁(yè)數(shù)： | 11/16頁(yè) |
| 文件大?。?/td> | 164K |
| 代理商： | ISPLSI1032E-80LT |
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11
Specifications
ispLSI 1032E
USEispLS 1032EAFORNEWDESGNS
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1. Calculations are based upon timing specifications for the ispLSI 1032E-125.
ispLSI 1032E Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
0491
Feedback
Reg 4 PT Bypass
#35
20 PT
XOR Delays
Control
PTs
#44 - 46
Input
Register
RST
Clock
Distribution
I/O Pin
(Input)
Y0
Y1,2,3
Q
GRP4
#30
GLB Reg Bypass
#39
ORP Bypass
#48
Q
RST
RE
OE
CK
I/O Reg Bypass
#22
I/O Cell
ORP
GLB
GRP
I/O Cell
#23 - 27
#34 Comb 4 PT Bypass
#36 - 38
#55 - 58
#54
#53
#47
Reset
Ded. In
GOE 0,1
#28
#59
#59
#40 - 43
#51, 52
#49, 50
GRP Loading
Delay
#29, 31 - 33
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
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Derivations of
t
su,
t
h and
t
co from the Clock GLB
2.9 ns
t
su
2.2 ns
Logic + Reg su - Clock (min)
(
t
iobp +
t
grp4 +
t
20ptxor) + (
t
gsu) – (
t
iobp +
t
grp4 +
t
ptck(min))
(#22 + #30 + #37) + (#40) – (#22 + #30 + #46)
(0.3 + 2.0 + 5.0) + (0.1) – (0.3 + 2.0 + 2.9)
t
h
Clock (max) + Reg h - Logic
(
t
iobp +
t
grp4 +
t
ptck(max)) + (
t
gh) – (
t
iobp +
t
grp4 +
t
20ptxor)
(#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
(0.3 + 2.0 + 4.0) + (4.5) – (0.3 + 2.0 + 5.0)
t
co
Clock (max) + Reg co + Output
(
t
iobp +
t
grp4 +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#22 + #30 + #46) + (#42) + (#47 + #49)
(0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3)
Table 2-0042a/1032E
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t
su
Logic + Reg su - Clock (min)
(
t
iobp +
t
grp4 +
t
20ptxor) + (
t
gsu) – (
t
gy0(min) +
t
gco +
t
gcp(min))
(#22 + #30 + #37) + (#40) – (#54 + #42 + #56)
(0.3 + 2.0 + 5.0) + (0.1) – (1.4 + 2.3 + 0.8)
Clock (max) + Reg h - Logic
(
t
gy0(max) +
t
gco +
t
gcp(max)) + (
t
gh) – (
t
iobp +
t
grp4 +
t
20ptxor)
(#54 + #42 + #56) + (#41) – (#22 + #30 + #37)
(1.4 + 2.3 + 1.8) + (4.5) – (0.3 + 2.0 + 5.0)
t
h
t
co
Clock (max) + Reg co + Output
(
t
gy0(max) +
t
gco +
t
gcp(max)) + (
t
gco) + (
t
orp +
t
ob)
(#54 + #42 + #56) + (#42) + (#47 + #49)
(1.4 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3)
3.5 ns
10.9 ns
2.7 ns
5.5 ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPLSI1032E-90LJ | In-System Programmable High Density PLD |
| ISPLSI1032E-90LJ | High-Density Programmable Logic |
| ISPLSI1032E-90LT | In-System Programmable High Density PLD |
| ISPLSI1032E-90LT | High-Density Programmable Logic |
| ISPLSI1032E-100LT | In-System Programmable High Density PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI1032E80LTI | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1032E80LTN | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1032E80LTNI | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1032E90LJ | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Electrically-Erasable Complex PLD |
| ISPLSI1032E-90LJ | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
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