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參數(shù)資料
| 型號： | ISPLSI1032E-70LTI |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High-Density Programmable Logic |
| 中文描述： | 高密度可編程邏輯 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 301K |
| 代理商： | ISPLSI1032E-70LTI |
12
Specifications
ispLSI and pLSI 1032E
Maximum GRP Delay vs GLB Loads
GLB Load
3.0
5.0
1
8
16
32
G
4.0
4
2.0
6.0
GRP/GLB/1032E
ispLSI and pLSI 1032E-70
ispLSI and pLSI 1032E-90/100
ispLSI and pLSI 1032E-80
ispLSI and pLSI 1032E-125
1.0
Power Consumption
Figure 3. Typical Device Power Consumption vs fmax
Power consumption in the ispLSI and pLSI 1032E device
depends on two primary factors: the speed at which the
device is operating, and the number of product terms
used. Figure 3 shows the relationship between power
and operating speed.
0127/1032E
f
max (MHz)
Notes: Configuration of eight 16-bit counters
Typical current at 5V, 25
°
C
100
200
300
0
20
40
60
80
100
I
C
ispLSI and pLSI 1032E
250
150
350
125
150
I can be estimated for the ispLSI and pLSI 1032E using the following equation:
I (mA) = 15 + (# of PTs * 0.59) + (# of nets * Max freq * 0.0078)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The I estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB
loads on average exists. These values are for estimates only. Since the value of I is sensitive to operating
conditions and the program in the device, the actual I should be verified.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISP1032E | High-Density Programmable Logic |
| ISPLSI1032E-125LJ | In-System Programmable High Density PLD |
| ISPLSI1032E-125LJ | High-Density Programmable Logic |
| ispLSI1032EA-100LT100 | In-System Programmable High Density PLD |
| ISPLSI1032EA-200LT100 | In-System Programmable High Density PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI1032E70LTN | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ispLSI1032E-70LTN | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI1032E70LTNI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ispLSI1032E-70LTNI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI1032E80LJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
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