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參數(shù)資料
| 型號(hào)： | ISPLSI1032-90LT |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類(lèi)： | PLD |
| 英文描述： | In-System Programmable High Density PLD |
| 中文描述： | EE PLD, 17 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大?。?/td> | 226K |
| 代理商： | ISPLSI1032-90LT |
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Specifications
ispLSI 1032
6
U0
–
–
–
U0E
U0E
–
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Internal Timing Parameters
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
7.3
1.3
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1.3
6.0
–
–
4.6
–
–
2.7
4.0
–
–
4.0
3.3
5.3
2.0
2.7
4.0
5.0
6.0
10.6
8.6
9.3
10.6
12.7
1.3
–
–
2.7
3.3
13.3
12.0
9.9
3.3
0.7
MIN. MAX.
DESCRIPTION
PARAMETER
UNITS
-60
Inputs
t
iobp
t
iolat
t
iosu
t
ioh
t
ioco
t
ior
t
din
GRP
t
grp1
t
grp4
t
grp8
t
grp12
t
grp16
t
grp32
GLB
t
4ptbp
t
1ptxor
t
20ptxor
t
xoradj
t
gbp
t
gsu
t
gh
t
gco
t
gr
t
ptre
t
ptoe
t
ptck
ORP
t
orp
t
orpbp
#
2
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
I/O Register Bypass
I/O Latch Delay
I/O Register Setup Time before Clock
I/O Register Hold Time after Clock
I/O Register Clock to Out Delay
I/O Register Reset to Out Delay
Dedicated Input Delay
GRP Delay, 1 GLB Load
GRP Delay, 4 GLB Loads
GRP Delay, 8 GLB Loads
GRP Delay, 12 GLB Loads
GRP Delay, 16 GLB Loads
GRP Delay, 32 GLB Loads
4 Product Term Bypass Path Delay
1 Product Term/XOR Path Delay
20 Product Term/XOR Path Delay
XOR Adjacent Path Delay
3
GLB Register Bypass Delay
GLB Register Setup Time before Clock
GLB Register Hold Time after Clock
GLB Register Clock to Output Delay
GLB Register Reset to Output Delay
GLB Product Term Reset to Register Delay
GLB Product Term Output Enable to I/O Cell Delay
GLB Product Term Clock Delay
ORP Delay
ORP Bypass Delay
–
–
5.5
1.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1.0
4.5
–
–
–
3.5
–
–
2.0
3.0
–
–
3.0
2.5
4.0
1.5
2.0
3.0
3.8
4.5
8.0
6.5
7.0
8.0
9.5
1.0
–
–
2.0
2.5
10.0
9.0
7.5
2.5
0.5
MIN. MAX.
-80
–
–
4.8
2.1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1.2
3.6
–
2.8
–
–
1.6
2.4
–
–
2.4
2.8
3.2
1.2
1.6
2.4
3.0
3.6
6.4
5.7
7.0
8.2
0.8
–
–
1.6
2.0
8.0
7.8
6.0
2.4
0.4
MIN. MAX.
-90
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPLSI1032E-100LJ | In-System Programmable High Density PLD |
| ISPLSI1032E-80LJ | In-System Programmable High Density PLD |
| ISPLSI1032E-80LJ | High-Density Programmable Logic |
| ISPLSI1032E-80LT | In-System Programmable High Density PLD |
| ISPLSI1032E-80LT | High-Density Programmable Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI1032-90LT/833 | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1032-90LTI | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1032E | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1032E_06 | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1032E100LJ | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Electrically-Erasable Complex PLD |
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