參數(shù)資料
型號： ISPLSI1016E-80LT44
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： In-System Programmable High Density PLD
中文描述： EE PLD, 18.5 ns, PQFP44
封裝： TQFP-44
文件頁數(shù)： 10/12頁
文件大?。?/td> 150K
代理商： ISPLSI1016E-80LT44
10
Specifications
ispLSI 1016E
Input - This pin performs two functions. When
ispEN
is logic low, it functions
as an input pin to load programming data into the device. It is a dedicated
input pin when
ispEN
is logic high.SDI/IN0 also is used as one of the two
control pins for the isp state machine.
Input - This pin performs two functions. When
ispEN
is logic low, it functions
as a pin to control the operation of the isp state machine. It is a dedicated
input pin when
ispEN
is logic high.
Output/Input - This pin performs two functions. When
ispEN
is logic low, it
functions as an output pin to read serial shift register data. It is a dedicated
input pin when
ispEN
is logic high.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all the GLBs on the device.
This pin performs two functions:
- Dedicated clock input. This clock input is brought into the Clock
Distribution Network, and can optionally be routed to any GLB and/or
I/O cell on the device.
- Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO and
SCLK controls become active.
This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.
Input/Output Pins - These are the general purpose I/O pins used by the logic
array.
NAME
Table 2-0002C-16-isp
DESCRIPTION
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
GOE 0/IN 3
2
Y1/
RESET
Y0
SDI/IN 0
1
ispEN
MODE/IN 2
1
GND
Vcc
VCC
SDO/IN 1
1
Input - This pin performs two functions. When
ispEN
is logic low, it
functions as a clock pin for the Serial Shift Register. It is a dedicated clock
input when
ispEN
is logic high. This clock input is brought into the Clock
Distribution Network, and can optionally be routed to any GLB and/or I/O
cell on the device.
SCLK/Y2
1
Ground (GND)
PLCC
PIN NUMBERS
15,
19,
25,
29,
37,
41,
3,
7,
16,
20,
26,
30,
38,
42,
4,
8,
17,
21,
27,
31,
39,
43,
5,
9,
18,
22,
28,
32,
40,
44,
6,
10
2
35
11
14
13
36
1,
12,
24
33
23
34
1. Pins have dual function capability.
2. Pins have dual function capability which is software selectable.
TQFP
PIN NUMBERS
9,
13,
19,
23,
31,
35,
41,
1,
10,
14,
20,
24,
32,
36,
42,
2,
11,
15,
21,
25,
33,
37,
43,
3,
12,
16,
22,
26,
34,
38,
44,
4
40
29
5
8
7
30
17,
6,
18
27
39
28
Pin Description
相關(guān)PDF資料
PDF描述
ISPLSI1016E-80LT44I In-System Programmable High Density PLD
ISPLSI1016E-100LJ In-System Programmable High Density PLD
ISPLSI1016E-100LT44 In-System Programmable High Density PLD
ISPLSI1024EA-100LT100 In-System Programmable High Density PLD
ISPLSI1024EA-125LT100 In-System Programmable High Density PLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPLSI1016E80LT44I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD
ispLSI1016E-80LT44I 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ISPLSI1016E80LTN44 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD
ISPLSI1016E80LTN44I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD
ispLSI1016E-80LTN44I 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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