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參數(shù)資料
| 型號： | ISPLSI1016E-125LJ |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | In-System Programmable High Density PLD |
| 中文描述： | EE PLD, 10 ns, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 150K |
| 代理商： | ISPLSI1016E-125LJ |
6
Specifications
ispLSI 1016E
Internal Timing Parameters
1
t
iobp
t
iolat
t
iosu
t
ioh
t
ioco
t
ior
t
din
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Lattice hard macros.
Table 2-0036-16/125,100, 80
Inputs
UNITS
-125
MIN.
-100
MIN.
MAX.
MAX.
DESCRIPTION
#
2
PARAMETER
22 I/O Register Bypass
23 I/O Latch Delay
24 I/O Register Setup Time before Clock
25 I/O Register Hold Time after Clock
26 I/O Register Clock to Out Delay
27 I/O Register Reset to Out Delay
28 Dedicated Input Delay
–
–
–
–
0.4
2.4
–
–
5.0
5.0
2.6
ns
ns
ns
ns
ns
ns
ns
t
grp1
t
grp4
t
grp8
29 GRP Delay, 1 GLB Load
30 GRP Delay, 4 GLB Loads
31 GRP Delay, 8 GLB Loads
–
–
–
–
–
–
1.9
2.2
2.5
ns
ns
ns
GLB
t
4ptbpc
t
4ptbpr
t
1ptxor
t
20ptxor
t
xoradj
t
gbp
t
gsu
t
gh
t
gco
t
gro
t
ptre
t
ptoe
t
ptck
ORP
t
orp
t
orpbp
36 1 Product Term/XOR Path Delay
37 20 Product Term/XOR Path Delay
38 XOR Adjacent Path Delay
39 GLB Register Bypass Delay
–
–
–
–
–
–
–
–
6.1
6.1
6.6
1.6
ns
ns
ns
ns
40 GLB Register Setup Time before Clock
41 GLB Register Hold Time after Clock
–
–
0.2
2.5
–
–
ns
ns
42 GLB Register Clock to Output Delay
–
–
1.9
ns
3
43 GLB Register Reset to Output Delay
44 GLB Product Term Reset to Register Delay
45 GLB Product Term Output Enable to I/O Cell Delay
46 GLB Product Term Clock Delay
–
–
–
–
–
–
6.3
5.1
7.1
5.3
ns
ns
ns
ns
4.8
0.3
1.8
–
–
4.0
4.0
2.2
GRP
1.8
1.9
2.1
34 4 Product Term Bypass Path Delay (Combinatorial)
35 4 Product Term Bypass Path Delay (Registered)
–
–
–
–
5.7
5.6
ns
ns
4.4
4.4
4.4
1.0
3.9
3.9
0.2
1.5
1.8
4.4
3.5
5.5
3.5
3.2
47 ORP Delay
48 ORP Bypass Delay
–
–
–
–
1.0
0.0
ns
ns
1.0
0.0
3.0
-0.3
–
–
–
3.5
-0.4
–
–
–
-80
MIN. MAX.
–
–
–
–
–
–
–
–
–
–
–
–
6.8
–
–
–
–
–
–
–
–
–
–
0.6
3.6
4.5
-0.6
7.5
7.5
3.9
2.9
3.3
3.8
7.1
8.2
8.3
1.9
8.1
7.3
-0.6
4.3
2.9
7.0
7.2
9.7
7.5
1.5
0.0
t
grp16
32 GRP Delay, 16 GLB Loads
–
–
3.1
ns
2.4
–
–
–
4.7
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| ISPLSI1016E-125LT44 | In-System Programmable High Density PLD |
| ISPLSI1016E-80LJ | In-System Programmable High Density PLD |
| ISPLSI1016E-80LJI | In-System Programmable High Density PLD |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI1016E125LJI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1016E-125LJI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1016E125LJN | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ispLSI1016E-125LJN | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI1016E125LJNI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
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