參數(shù)資料
型號： ISPL1048E-90LT
廠商： Lattice Semiconductor Corporation
英文描述： High-Density Programmable Logic
中文描述： 高密度可編程邏輯
文件頁數(shù)： 11/16頁
文件大?。?/td> 158K
代理商： ISPL1048E-90LT
Specifications
ispLSI 1048E
11
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
0491
Feedback
Reg 4 PT Bypass
#35
20 PT
XOR Delays
Control
PTs
#44 - 46
Input
RST
DiClock
I/O Pin
(Input)
Y0
Y1,2,3
D
Q
GRP4
#30
GLB Reg Bypass
#39
ORP Bypass
#48
D
Q
RST
RE
OE
CK
I/O Reg Bypass
#22
I/O Cell
ORP
GLB
GRP
I/O Cell
#23 - 27
#34 Comb 4 PT Bypass
#36 - 38
#55 - 58
#54
#53
#47
Reset
Ded. In
GOE 0,1
#28
#59
#59
#40 - 43
#51, 52
#49, 50
GRP Loading
Delay
#29, 31-33
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
1
=
=
=
=
2.2 ns
(0.3 + 2.0 + 5.0) + (0.1) – (0.3 + 2.0 + 2.9)
t
su
Logic + Reg su - Clock (min)
(
t
iobp +
t
grp4 +
t
20ptxor) + (
t
gsu) – (
t
iobp +
t
grp4 +
t
ptck(min))
(#22 + #30 + #37) + (#40) – (#22 + #30 + #46)
=
=
=
=
t
h
Clock (max) + Reg h - Logic
(
t
iobp +
t
grp4 +
t
ptck(max)) + (
t
gh) – (
t
iobp +
t
grp4 +
t
20ptxor)
(#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
(0.3 + 2.0 + 4.0) + (4.5) – (0.3 + 2.0 + 5.0)
=
=
=
=
t
co
Clock (max) + Reg co + Output
(
t
iobp +
t
grp4 +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#22 + #30 + #46) + (#42) + (#47 + #49)
(0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3)
Table 2-0042/1048E
Derivations of
t
su,
t
h and
t
co from the Clock GLB
1
=
=
=
=
t
su
Logic + Reg su - Clock (min)
(
t
iobp +
t
grp4 +
t
20ptxor) + (
t
gsu) – (
t
gy0(min) +
t
gco +
t
gcp(min))
(#22 + #30 + #37) + (#40) – (#54 + #42 + #56)
(0.3 + 2.0 + 5.0) + (0.1) – (0.9 + 2.3 + 0.8)
=
=
=
=
t
h
Clock (max) + Reg h - Logic
(
t
gy0(max) +
t
gco +
t
gcp(max)) + (
t
gh) – (
t
iobp +
t
grp4 +
t
20ptxor)
(#54 + #42 + #56) + (#41) – (#22 + #30 + #37)
(0.9 + 2.3 + 1.8) + (4.5) – (0.3 + 2.0 + 5.0)
=
=
=
=
t
co
Clock (max) + Reg co + Output
(
t
gy0(max) +
t
gco +
t
gcp(max)) + (
t
gco) + (
t
orp +
t
ob)
(#54 + #42 + #56) + (#42) + (#47 + #49)
(0.9 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3)
3.5 ns
10.9 ns
3.4 ns
2.2 ns
9.6 ns
1. Calculations are based upon timing specifications for the ispLSI 1048E-125.
ispLSI 1048E Timing Model
相關(guān)PDF資料
PDF描述
ISPL1048E-90LTI High-Density Programmable Logic
ISP1048E High-Density Programmable Logic
ISPLSI1016EA-100LJ44 In-System Programmable High Density PLD
ISPLSI1016EA-100LT44 In-System Programmable High Density PLD
ISPLSI1016EA-125LJ44 In-System Programmable High Density PLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPL1048E-90LTI 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic
ISPLS1101690LT 制造商:Lattice Semiconductor Corporation 功能描述:
ISPLS-3192-100LB272 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述:
ISPLSI 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Lattice Semiconductor Corporation 功能描述:
ispLSI 1016-110LJ 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*