- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄384536 > ISPL1048E-50LQ (Lattice Semiconductor Corporation) High-Density Programmable Logic PDF資料下載
參數(shù)資料
| 型號(hào)： | ISPL1048E-50LQ |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High-Density Programmable Logic |
| 中文描述： | 高密度可編程邏輯 |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大?。?/td> | 158K |
| 代理商： | ISPL1048E-50LQ |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)當(dāng)前第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)
Specifications
ispLSI 1048E
6
U4
–
NES
24.0
16.0
16.0
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
t
pd2
f
max (Int.)
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
UNITS
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model
in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030B/1048E
1
4
3
1
( )
-50
MIN. MAX.
–
–
50.0
DESCRIPTION
#
2
PARAMETER
A
A
A
1
2
3
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback
20.0
24.5
ns
ns
MHz
–
–
–
–
4
5
6
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
GLB Reg. Setup Time before Clock,4 PT Bypass
–
–
–
MHz
MHz
ns
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
–
ns
–
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
–
ns
–
–
–
A
–
B
C
B
C
9
GLB Reg. Setup Time before Clock
GLB Reg. Clock to Output Delay
GLB Reg. Hold Time after Clock
Ext. Reset Pin to Output Delay
Ext. Reset Pulse Duration
Input to Output Enable
Input to Output Disable
Global OE Output Enable
Global OE Output Disable
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
13
14
15
16
17
–
–
–
–
–
–
t
wh
t
wl
t
su3
t
h3
–
–
18
19
External Synchronous Clock Pulse Duration, High
External Synchronous Clock Pulse Duration, Low
6.5
6.5
ns
ns
–
20
I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3)
–
ns
–
21
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
–
ns
42.0
77.0
12.0
0.0
14.5
13.0
6.5
0.0
9.5
12.0
20.5
24.0
–
–
( )
1
-70
MIN. MAX.
–
–
70.0
15.0
18.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
5.0
5.0
–
–
56.0
100.0
9.0
0.0
11.0
0.0
10.0
4.0
0.0
7.0
9.0
15.0
18.0
18.0
12.0
12.0
–
–
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPL1048E-50LT | High-Density Programmable Logic |
| ISPL1048E-50LTI | High-Density Programmable Logic |
| ISPL1048E-70LQ | High-Density Programmable Logic |
| ISPL1048E-70LT | High-Density Programmable Logic |
| ISPL1048E-70LTI | High-Density Programmable Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPL1048E-50LQI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
| ISPL1048E-50LT | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
| ISPL1048E-50LTI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
| ISPL1048E-70LQ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
| ISPL1048E-70LQI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。