參數(shù)資料
型號(hào): ISP1520BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus hub controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁(yè)數(shù): 37/51頁(yè)
文件大小: 259K
代理商: ISP1520BD
Philips Semiconductors
ISP1520
Hi-Speed USB hub controller
Product data
Rev. 02 — 04 May 2004
37 of 51
9397 750 11689
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table 43:
V
CC
= 3.0 V to 3.6 V; T
amb
= 0
°
C to 70
°
C; test circuit
Figure 21
; unless otherwise specified.
Symbol
Parameter
Driver characteristics
t
HSR
rise time
t
HSF
fall time
Clock timing
t
HSDRAT
data rate
t
HSFRAM
microframe interval
t
HSRFI
consecutive microframe interval
difference
Dynamic characteristics: high-speed source electrical characteristics
Conditions
Min
Typ
Max
Unit
10 % to 90 %
90 % to 10 %
500
500
-
-
-
-
ps
ps
479.76
124.9375 -
1
-
480.24
125.0625
four high-speed
bit times
Mbit/s
μ
s
ns
-
Table 44:
V
CC
= 3.0 V to 3.6 V; T
amb
= 0
°
C to 70
°
C; test circuit
Figure 22
; unless otherwise specified.
Symbol
Parameter
Driver characteristics
t
FR
rise time
Dynamic characteristics: full-speed source electrical characteristics
Conditions
Min
Typ
Max
Unit
C
L
= 50 pF; 10 % to 90 % of
|
V
OH
V
OL
|
C
L
= 50 pF; 90 % to 10 % of
|
V
OH
V
OL
|
4
-
20
ns
t
FF
fall time
4
-
20
ns
t
FRFM
differential rise and fall time
matching
driver output resistance
[1]
90
-
111.1
%
Z
DRV
for the driver that is not
high-speed capable
28
-
44
V
CRS
Data source timing
[2]
t
DJ1
output signal crossover voltage
[1][2]
1.3
-
2.0
V
source differential jitter for
consecutive transitions
source differential jitter for paired
transitions
source SE0 interval of EOP
source differential data-to-EOP
transition skew
Receiver timing
[2]
t
JR1
receiver data jitter tolerance for
consecutive transitions
t
JR2
receiver data jitter tolerance for
paired transitions
t
FEOPR
receiver SE0 width
see
Figure 10
[1]
3.5
-
+
3.5
ns
t
DJ2
see
Figure 10
[1]
4
-
+
4
ns
t
FEOPT
t
FDEOP
see
Figure 11
see
Figure 11
160
2
-
-
175
+
5
ns
ns
see
Figure 12
18.5
-
+
18.5
ns
see
Figure 12
9
-
+
9
ns
accepted as EOP; see
Figure 11
rejected as EOP; see
Figure 13
82
-
-
ns
t
FST
width of SE0 interval during
differential transaction
Hub timing (downstream ports configured as full-speed)
[2]
t
FHDD
hub differential data delay (without
cable)
-
-
14
ns
see
Figure 14
; C
L
= 0 pF
-
-
44
ns
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