參數(shù)資料
型號(hào)： ISP1161A1BM
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Universal Serial Bus single-chip host and device controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁(yè)數(shù)： 17/127頁(yè)
文件大?。?/td> 2762K
代理商： ISP1161A1BM
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Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
17 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
8.4 Microprocessor read/write ISP1161’s internal FIFO buffer RAM by
PIO mode
Since ISP1161’s internal memory is structured as a FIFO buffer RAM, the FIFO buffer
RAM is mapped to dedicated register fields. Therefore, accessing ISP1161’s internal
FIFO buffer RAM is just like accessing the internal control registers in multiple data
phases.
Figure 17
shows a complete access cycle of ISP1161’s internal FIFO buffer RAM. For
a write cycle, the microprocessor first writes the FIFO buffer RAM’s command code to
the command port, and then writes the data words one by one to the data port until
half of the transfer’s byte count is reached. The HcTransferCounter register (22H -
Read, A2H - Write) is used to specify the byte count of a FIFO buffer RAM’s read
cycle or write cycle. Every access cycle must be in the same access direction. The
read cycle procedure is similar to the write cycle.
For ISP1161 DC’s FIFO buffer RAM access, see
Section 11
.
8.5 Microprocessor read/write ISP1161’s internal FIFO buffer RAM by
DMA mode
The DMA interface between a microprocessor and ISP1161 is shown in
Figure 10
.
When doing a DMA transfer, at the beginning of every burst the ISP1161 outputs a
DMA request to the microprocessor via the DREQ pin (DREQ1 for HC, DREQ2 for
DC). After receiving this signal, the microprocessor will reply with a DMA
acknowledge to ISP1161 via the DACK pin (DACK1 for HC, DACK2 for DC), and at
the same time, do the DMA transfer through the data bus. For normal DMA mode, the
Fig 16. Accessing ISP1161 DC control registers.
Signals
Valid status
0
11
CS
A1, A0
Valid status
0
10
Valid status
0
10
RD = 1,
WR = 0
data bus
Command code
Register data
(upper word)
Register data
(lower word)
MGT940
RD, WR
RD = 0 (read) or
WR = 0 (write)
RD = 0 (read) or
WR = 0 (write)
Fig 17. ISP1161’s internal FIFO buffer RAM access cycle.
MGT941
read/write data
#1 (16 bits)
FIFO buffer RAM access cycle (transfer counter = 2N)
t
read/write data
#2 (16 bits)
read/write data
#N (16 bits)
write command
(16 bits)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1161A1BM,518 功能描述:USB 接口集成電路 USB1.1 HOST/DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161A1BM,551 功能描述:USB 接口集成電路 USB HOST+DEV CTRLR RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161A1BM,557 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161A1BMGA 功能描述:IC USB HOST/DEVICE CTRLR 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
ISP1161A1BM-S 功能描述:USB 接口集成電路 USB HOST+DEV CTRLR RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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