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ISLA224S
8
FN7911.2
April 25, 2013
Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
CMOS INPUTS
Input Current High (RESETN)
IIH
VIN = 1.8V
1
10
A
Input Current Low (RESETN)
IIL
VIN = 0V
-25
-12
-7
A
Input Current High (SDIO, SCL, SDA SCLK)
IIH
VIN = 1.8V
4
12
A
Input Current Low (SDIO, SCL, SDA SCLK)
IIL
VIN = 0V
-600
-400
-300
A
Input Current High (CSB)
IIH
VIN = 1.8V
40
52
70
A
Input Current Low (CSB)
IIL
VIN = 0V
1
10
A
Input Voltage High (SDIO, RESETN)
VIH
1.17
V
Input Voltage Low (SDIO, RESETN)
VIL
0.63
V
Input Current High (NAPSLP, CLKDIV) (Note
11)IIH
19
25
30
A
Input Current Low (NAPSLP, CLKDIV)
IIL
--30
-25
-19
A
Input Capacitance
CDI
4pF
LVDS INPUTS (SYNCP, SYNCN)
Input Common Mode Range
VICM
825
1575
mV
Input Differential Swing (peak-to-peak, single-ended)
VID
250
450
mV
Input Pull-up and Pull-down Resistance
RIpu
100
k
CML OUTPUTS
Output Common Mode Voltage
1.14
V
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
ADC OUTPUT
Aperture Delay
tA
190
ps
RMS Aperture Jitter
jA
100
fs
Synchronous Clock Divider Reset Recovery Time (Note
12)
tRSTRT
DLL recovery
time after
Synchronous
Reset
250
s
Latency (ADC Pipeline Delay)
L
10
cycles
Overvoltage Recovery
tOVR
1cycles
SERDES
PLL Lock Time
250
s
PLL Bandwidth
2.2
MHz
Added Random Jitter
5ps
RMS
Added Deterministic Jitter
7ps P-P
Maximum Input Sample Clock Total Jitter to Maintain SERDES
BER <1E-12
Integrated from
1kHz to 10MHz
offset from
carrier
5ps rms